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5:00 PM
Intro
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Marcel Stanitzki
(DESY)
Richard Nickerson
(Oxford University)
Vitaliy Fadeyev
(SCIPP / UCSC)
-
5:05 PM
Architectural chip design
-
Herve Grabas
(UCSC)
-
5:15 PM
Testing HVStripV1
-
Craig Buttar
(University of Glasgow)
Dopke Jens
(RAL)
Jaya John John
(Oxford)
KESTUTIS KANISAUSKAS
Luigi Vigani
(Oxford)
Todd Huffman
(Oxford University)
-
5:30 PM
Testing CHESS1
-
Igor Mandic
-
5:40 PM
Testing CHESS1 Active circuitry
-
Herve Grabas
(UCSC)
-
5:50 PM
Status of test kit and its distribution; CHESS daughter board
-
Huffman Todd
Jaya John John
(Oxford)
-
6:10 PM
Discussion
