ATLAS Strip CMOS Design Review (CHESS-2)
Wednesday 1 July 2015 -
16:00
Monday 29 June 2015
Tuesday 30 June 2015
Wednesday 1 July 2015
16:00
Design overview and architecture
-
Herve Grabas
(
UCSC
)
Pietro Caragiulo
(
SLAC
)
Design overview and architecture
Herve Grabas
(
UCSC
)
Pietro Caragiulo
(
SLAC
)
16:00 - 16:15
16:15
Pixel
-
Herve Grabas
(
UCSC
)
Pixel
Herve Grabas
(
UCSC
)
16:15 - 16:35
Analog description and simulation results
16:35
Strip encoding
-
Herve Grabas
(
UCSC
)
Strip encoding
Herve Grabas
(
UCSC
)
16:35 - 16:50
Encoding of the hit in the row of 32 pixels and simulation results
16:50
Hit Encoding and Readout Blocks
-
Pietro Caragiulo
(
SLAC
)
Hit Encoding and Readout Blocks
Pietro Caragiulo
(
SLAC
)
16:50 - 17:15
Encoding architecture and results. Readout block and LVDS interface.
17:15
ASIC Configuration and Calibration
-
Pietro Caragiulo
(
SLAC
)
ASIC Configuration and Calibration
Pietro Caragiulo
(
SLAC
)
17:15 - 17:35
Description of the serial interface, control unit, global register and DACs
17:35
Test structures
-
Herve Grabas
(
UCSC
)
Test structures
Herve Grabas
(
UCSC
)
17:35 - 17:55
Test structure in CHESS2