7–10 Dec 2015
DESY
Europe/Berlin timezone

2800 MB/s Heterogeneous Data Processing for a 4-channel, 5.6 Gbps Wind-LIDAR-System

9 Dec 2015, 17:15
15m
CFEL (DESY)

CFEL

DESY

Building 99, Notkestraße 85, 22607 Hamburg

Speaker

Mr Karl Judex (Industry)

Description

The bistatic Wind-LIDAR-System developed by German Physikalische-Technische Bundesanstalt (PTB) is a great practical example on how MicroTCA systems can solve computational challenges: With 4 analog channels, each sampled at 350M samples per second with 16 bits per sample, 2800 MB/s of streaming data can be tackled with heterogeneous compute elements. As a first-stage data processing instance we selected an FPGA, a Xilinx Virtex-7 690T with multiple high-speed SerDes interfaces. The targeted measuring principle requires a deterministic latency between the generated waveforms sent to the DACs and the corresponding input data. This is guaranteed by using the JESD204B protocol to transfer the data between the FPGA and the ADC/DAC. Our presentation will elaborate on the design choices and observations when using JESD204B within an FPGA environment. The FPGA has the task to essentially reduce the data rate and to transport the data to the DSPs, TMS320C6678 from TI, for subsequent data analysis. In our presentation we will highlight the custom signal processing implemented inside the FPGA which effectively reduces the data rate down to 50M samples per second with 32 bits per sample, per channel. Data transmission from the FPGA to the multi-DSP subcomponent is done via PCIe Gen3 x4 at 200MB/s per channel. We will demonstrate how we used a MicroTCA backplane for PCIe and go into details of a custom protocol on top of PCIe which mimics the queue aspects of modern NVMe SSDs to reduce latency and implementation effort. We will then discuss the architecture of three separate DSP, two DSP for further processing per channel followed by overall processing done in the third DSP, again reducing the amount of data. The DSP themselves are interconnected via PCIe Gen2 x2, the third DSP also connects via Gigabit Ethernet on the MicroTCA backplane to transport data at the final rate of 20MB/s to a PC component featuring an Intel i7 CPU. Finally, Ethernet on the MicroTCA backplane is used for system-wide setup and control.

Primary author

Mr Karl Judex (Industry)

Co-authors

Mr Joachim Förster (Missing Link Electronics) Dr Michael Eggert (Physikalisch-Technische Bundesanstalt) Mr Thomas Decker (Missing Link Electronics)

Presentation materials