Design and Validation of Multi-Gigabit Systems - Challenges of Embedded Design and High-Speed Interconnect

Tuesday 22 Oct 2019, 09:00 → 16:30 Europe/Berlin

Seminar room FLASH (Building 28C)

Thomas Walter (DESY)

Design and Validation of Multi-Gigabit Systems - Challenges of Embedded Design and High-Speed Interconnect

The seminar “Design and Validation of Multi-Gigabit Systems” - Challenges of Embedded Design and High-Speed Interconnect is part of an educational event series hosted by the MicroTCA Technology Lab (A Helmholtz Innovation Lab) at DESY in cooperation with industry partners.

This seminar, featuring experts from both Rohde & Schwarz and DESY, explores the challenges of embedded system design on board level and introduces strategies for high-speed signal measurement and analysis using state-of-the-art measurement technology. The following subjects will be covered in detail:

•             Analysis of Signal Integrity on High-Speed Interfaces

•             Design and Evaluation of Multi-Gigabit Transmission Lines

•             Power Integrity and Power Supply Analysis

•             PCI Express

 

Live demonstrations will include Eye diagrams, TDR, Oscilloscope vs. VNA measurement scenarios and impedance plots. A final Q&A session will conclude this seminar.

Event Host:  DESY

 

09:00 → 09:45 MicroTCA Technology Lab (3/304) – “Open Lab”

10:00 → 10:15 Welcome and Introduction

10:15 → 11:15 Analysis of Signal Integrity on High-Speed Interfaces

Speaker: Alexander Küllmer (Rohde & Schwarz)

11:15 → 11:30 Coffee Break

11:30 → 12:30 Design and Evaluation of Multi-Gigabit Transmission Lines

Speaker: Michael Fenner (DESY)

12:30 → 13:15 Lunch Break

13:15 → 14:15 Power Integrity and Power Supply Analysis

Speaker: Alexander Küllmer (Rohde & Schwarz)

14:15 → 14:30 Coffee Break

14:30 → 15:30 PCI Express – Architecture, Implementation and Measurement

Speaker: Mr Jan Marjanovic (DESY)

Slides wsMGT_2019_marjanovic_pcie.pdf

15:30 → 16:15 Q&A

16:15 → 16:30 Recap & Closeout