Name: 2nd PUNCH4NFDI TA5 Workshop on Machine Learning and Data Processing on FPGAs
Start: 2024-09-18T13:45:00+02:00
End: 2024-09-19T13:00:00+02:00
Location: TU Dresden

2nd PUNCH4NFDI TA5 Workshop on Machine Learning and Data Processing on FPGAs

from Wednesday 18 September 2024 (13:45) to Thursday 19 September 2024 (13:00)

Monday 16 September 2024
Tuesday 17 September 2024
Wednesday 18 September 2024
14:00
14:00 - 15:30
Room: REC B214
Contributions

14:00 Welcome to the Workshop

14:10 Experience with Xilinx Versal AI and status and news from Mainz group - Christian Kahra (Johannes Gutenberg - Universitaet Mainz)

14:35 Deep Learning for Real-time Classification of Astronomical Radio Signals: Current Status - Andrei Kazantsev (MPIfR)

15:00 Track reconstruction for the ATLAS Phase-II Event Filter using Graph Neural Networks on FPGAs - Sebastian Dittmeier (Physikalisches Institut, University of Heidelberg)
15:30 Coffee and Tea Break
Coffee and Tea Break
15:30 - 16:00
Room: REC B214
16:00
16:00 - 18:00
Room: REC B214
Contributions

16:00 Comparison of massively parallel and fully serial sorting on FPGAs - Emanuel Meuser (JGU Mainz)

16:20 CNNs for real time signal reconstruction in ATLAS LAr: Status and news from TU Dresden group - Johann Christoph Voigt

16:40 Hands-on Tutorial: Running Machine Learning models on an Alveo card using hls4ml - Yunpeng Men (MPIfR)
19:30 Dinner at a Dresden Restaurant (L'Osteria, Prager Strasse 1c )
Dinner at a Dresden Restaurant (L'Osteria, Prager Strasse 1c )
19:30 - 21:00
Room: REC B214
Thursday 19 September 2024
09:00
09:00 - 10:30
Room: REC B214
Contributions

09:05 High Level Synthesis with Siemens Catapult: Experience in ATLAS LAr - Nick Fritzsche (CERN)

09:35 OneAPI for Intel FPGAs - Johann Christoph Voigt

09:55 CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded System - Salim Ullah (Ruhr-Universität Bochum)
10:30 Coffee and Tea Break
Coffee and Tea Break
10:30 - 11:00
Room: REC B214
11:00
11:00 - 12:30
Room: REC B214
Contributions

11:00 Machine Learning on FPGAs for the CMS Level-1 Trigger - Finn Jonathan Labe (Universität Hamburg)

11:30 IPbus for FPGA slow control - Rainer Hentges (TU Dresden)

11:50 Summary discussion

Choose timezone