Name: Advanced Techniques in LLRF control for XFEL - Collaboration Workshop
Start: 2012-08-06T08:00:00+02:00
End: 2012-08-08T18:00:00+02:00
Location: Department of Microelectronics and Computer Science

Monday 6 August 2012
09:00
09:00 - 10:15
Room: Main Auditorium A1/A2
Contributions

09:00 Welcome and Introduction to Workshop - Andrzej NAPIERALSKI (TUL-DMCS)

09:10 Organization issues - Adam Piotrowski (Technical University of Lodz, DMCS)

09:15 LLRF System Status at CMTB & AMTF - Julien Branlard (DESY) Wojciech Cichalewski (TUL-DMCS)

09:45 LLRF System status REGAE & TDS Zeuthen - Matthias Hoffmann (DESY)
10:15 Coffee Break
Coffee Break
10:15 - 10:35
Room: Main Auditorium A1/A2
10:35
10:35 - 12:00
Room: Main Auditorium A1/A2
Contributions

10:35 EBPM System Status at FLASH - Uros Mavric (DESY)

10:55 LLRF Installation for the XFEL - Julien Branlard (DESY) Krzysztof Czuba Czuba (ISE)

11:25 Main changes XFEL LLRF System & HGF Validation fond perspectives - Holger Schlarb (DESY)
12:00 Lunch
Lunch
12:00 - 13:30
Room: Restaurant in Lodex
13:30
13:30 - 15:10
Room: Main Auditorium A1/A2
Contributions

13:30 MTCA.4 Platform Compatibility & Bugfixing - Uros Mavric (DESY)

13:50 Hardware & Firmware and Functionality of XxTIMER - Holger Kay (DESY)

14:10 KLM Status - Łukasz Butkowski (ISE)

14:30 uPS Design Status - Tomasz Jezynski (DESY)

14:50 FMC25 Design and Status - Stefan Korolczuk (The Andrzej Soltan Institute for Nuclear Studies (IPJ))
15:10 Coffee Break
Coffee Break
15:10 - 15:30
Room: Main Auditorium A1/A2
15:30
15:30 - 17:00
Room: Main Auditorium A1/A2
Contributions

15:30 Discussion: MCH, crates and power supply compatibility problems

15:35 Discussion: Bug reporting applications and procedures

15:40 Tutorial and discussion: how to set up MTCA system from scratch

15:45 Discussion: Other problems presented during MTCA.4 Platform Compatibility & Bugfixing presentation.
Tuesday 7 August 2012
08:30
08:30 - 10:00
Room: Main Auditorium A1/A2
Contributions

08:30 Functional block diagram for SIS8300 - Christian Schmidt (DESY)

08:45 SIS8300L Design Status - Frank Ludwig (DESY)

09:10 DWC8300FR 2.1 Design Status - Dominik Sikora (ISE, Warsaw University of Technology)

09:35 SIS8300 Firmware Status - Wojciech Jalmuzna (DMCS)
10:00 Coffee Break
Coffee Break
10:00 - 10:30
Room: Main Auditorium A1/A2
10:30
10:30 - 12:00
Room: Main Auditorium A1/A2
Contributions

10:30 Functional block diagram for uTC - Christian Schmidt (DESY)

10:45 uTC (V6) specification & resource budget - Dariusz Makowski Makowski (Tech. Univ. of Lodz, DMCS)

11:10 uVM Design Status - Igor Rutkowski (ISE, Warsaw University of Technology)

11:35 uTC Firmware Status - Wojciech Jalmuzna (DMCS)
12:00 Lunch
Lunch
12:00 - 13:30
Room: Restaurant in Lodex
13:30
13:30 - 15:00
Room: Main Auditorium A1/A2
Contributions

13:30 Tutorial and discussion: how to use DSP elements available in FPGA

13:35 Discussion: documentation for LLRF systems

13:40 Discussion: problems with timing modules

14:00 Discussion: uTC resources and specification
15:00 Coffee Break
Coffee Break
15:00 - 15:30
Room: Main Auditorium A1/A2
15:30
15:30 - 17:00
Room: Main Auditorium A1/A2
Contributions

15:30 uDS86800 + RTM Design Status - Samer Bou Habib (ISE, Warsaw University of Technology)

15:50 uRFB Design Status - Krzysztof Czuba (ISE, Warsaw University of Technology)

16:10 uLOG Design Status - Uros Mavric (DESY)

16:30 ZONE 3 Classification - Dariusz Makowski Makowski (Tech. Univ. of Lodz, DMCS)
18:30

18:30 - 21:00
Room: Restaurant "Gęsi Puch"
Wednesday 8 August 2012
08:00
08:00 - 09:40
Room: Main Auditorium A1/A2
Contributions

08:00 TMCB 2.0 Revision Status - Jaroslaw Szewinski (Soltan Institute for Nuclear Studies)

08:15 DCM Revision Status - Jan Piekarski (Warsaw University of Technology - Institute of Electronic Systems)

08:30 LOGM Revision Status - Mateusz Zukocinski (Warsaw University of Technology)

08:45 PZT Revision Status - Konrad Przygoda (TUL)

09:00 PSM Status - Daniel Kuehn (DESY)

09:10 MO Status - Lukasz Zembala (ISE, Warsaw University of Technology)

09:25 REFM Revision Status - Dominik Sikora (ISE, Warsaw University of Technology)
09:40 Coffee Break
Coffee Break
09:40 - 09:55
Room: Main Auditorium A1/A2
09:55
09:55 - 11:30
Room: Main Auditorium A1/A2
Contributions

09:55 Frontend server architecture and status - Adam Piotrowski (Technical University of Lodz, DMCS)

10:25 New Naming Convention for DOOCS Servers - Julien Branlard (DESY)

10:45 Automation for DOOCS servers for AMTF - Wojciech Cichalewski (TUL-DMCS)

11:00 Middle layer server for loaded Q characterization - Katarzyna Gnidzinska (DMCS/TUL)

11:10 Recent FB & calibration results at FLASH LLRF System - Sven Pfeiffer (DESY)
11:30 Lunch
Lunch
11:30 - 12:50
Room: Restaurant in Lodex
12:50
12:50 - 13:55
Room: Main Auditorium A1/A2
Contributions

12:50 Discussion: problems with jDDD

12:55 Discussion: universal server structure – how to develop server for different system