8-11 December 2014
DESY
Europe/Berlin timezone
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Contribution

DESY - FLASH II Hall
Software for MTCA.4

Status of MTCA Driver Development at DESY in Zeuthen

Speakers

  • Dr. Davit KALANTARYAN

Primary authors

Abstract content

Micro Telecommunications Computing Architecture (MicroTCA) is the new generation system, which should allow more stable and reliable control of the accelerator facilities such as FLASH at DESY and the European XFEL. The photo injector test facility at DESY, Zeuthen site (PITZ) is optimizing the electron source for the European XFEL. The MicroTCA system is also planned to be used at PITZ in order to have hardware/software configuration of different subsystems (RF system, interlock system, etc.) as close as possible to the European XFEL. At PITZ, it is not always possible to find the driver for MicroTCA devices, especially for homemade devices and sometimes additional work should be performed (special drivers have to be written) to adapt the system for PITZ. One of the examples is the PITZ timing system, where specific functionalities like bitwise writing, several register accesses in atomic manner, interrupt handling etc. are needed to handle the device. In general the aim is to have a driver that is able to handle different MicroTCA devices without slowing down the overall performance. Such a driver was developed at DESY-Zeuthen and is already in use for the PITZ timing devices. Some of frequently used functionalities are generalized for this driver. In addition the driver offers the hardware developer functionalities for debugging during hardware development stage. Adding new functionality for handling more devices and making optimizations are in progress. Using driver stacking makes possible to create specific drivers by adding only specific functionality required for each specific device, if it is not possible to handle the devices with specific functionalities. Some investigations have been done to select good synchronization mechanism for concurrent access to device registers. So far implemented functionalities like read and/or write arbitrary amount of data, bitwise writing arbitrary amount of bits from arbitrary number of registers etc. and ongoing implementation will be presented.