The idea of front-end digitization is to perform the digitization close to where the sensitive signal is generated. Digital signals provide large margins in time and amplitude, making them robust. An early digitization offers an intelligent processing and benefits from CMOS scaling. The challenge of this idea is high bandwidth. This approach is implemented in readout ASICs for two fast imagers, DSSC detector for single photon counting and dSiPM (digital silicon photomultiplier) for particle tracking. Unique features of these ASICs are analog signal processing, digitization, storage of 800 images on pixel level. The DSSC-readout ASIC contains 64 x 64 pixels of 204 x 236 µm² size and the dSiPM-prototype has 16 x 16 pixels with 50 x 57 µm² size. Both ASICs are designed in GF 130-nm CMOS technology. DSSC is using an 8-bit single-slope ADC for digitization. The small area requirements and less power consumption make this ADC compatible for pixel-level architectures. The features of the ADC are described and dynamic range, non-linearity and noise of 4096 ADCs operating in parallel at 4.5 MHz are characterized. The mean DNL-standard deviation of the full matrix is 0.4 LSB and the mean INL-standard deviation is 0.18 LSB. Cu-fluorescence measurements are performed on full-readout chip with DEPFET sensor for final XFEL-timing structure at PETRA-III beamline. Mean sensitivity of 0.72 keV/bin and mean noise of 80 e- has been extracted from the measurements. In dSiPM, digitization is done by an active quenching and recharging circuitry in each pixel sensing the avalanche current. The resulting signal can be used in its digital form for event discrimination. A 12-bit TDC is responsible for a cluster of 16 x 16 pixels and delivers the time stamps. Prototypes have been tested and the TDC performance at 3-MHz frame rate is characterized. The measured TDC resolution is 77 ps, DNL- and INL-standard deviation results in 0.15 LSB and 0.33 LSB, respectively. First dark-count rate measurements from sensor are presented.