Speaker
Dr
Michele Caselle
(KIT)
Description
A growing number of physics experiments requires DAQ systems with multi-Gbytes/s data-links. We developed a Direct Memory Access(DMA) engine compatible with the Xilinx PCI Express Gen2/3 core. Preliminary measurements with a Gen3 single-core have reached a throughput of up to 6.7 GBytes/s. We also intend to use this technology for direct communication between FPGA-based DAQ electronics and GPU memories (e.g. NVIDIA GPU-direct). This architecture finds its application in real-time DAQ systems and in low and high-level triggers for HEP experiments.
Primary author
Dr
Michele Caselle
(KIT)
Co-author
Mr
Lorenzo Rota
(KIT)
