Speaker
Ms
Roma Dasgupta
(AGH-UST)
Description
In the Silicon-On-Insulator CMOS structure the insulator layer is implemented between the handle wafer and the epitaxial silicon layer, which enables the design of a monolithic pixel detector without the need for bump-bonding. Due to the reduced detector volume there is much less particle scattering which results in a better spatial resolution. This is a significant advantage for vertex and tracking detectors at future linear colliders where high precision detectors are needed.
In this contribution preliminary test beam results of a SOI pixel detector designed by the AGH-UST and IFJ PAN groups in Cracow and fabricated in Lapis 0.2 um SOI CMOS technology are presented. The tested detector is produced on 500 um thick high resistivity floating zone wafer. The pixel architecture is based on source-follower and its size is 30x30 um. The test beam data was recorded in the 120 GeV pion beam at the SPS H6 beamline at CERN in collaboration with the CLICdp collaboration in June-August 2016.
The data was analysed in order to compute the spatial resolution of the detector. The analysis procedure includes pedestal and noise calculation, correlation with the Timepix3 reference telescope, different cluster reconstruction algorithms, as well as alignment and eta correction.
Preliminary results give a spatial resolution of about 4 um in both X and Y directions. The results are presented for different back bias voltages.
Primary authors
Ms
Roma Dasgupta
(AGH-UST)
Mr
Szymon Bugiel
(AGH-UST)
