Design and Validation of Multi-Gigabit Systems - Challenges of Embedded Design and High-Speed Interconnect

Name: Design and Validation of Multi-Gigabit Systems - Challenges of Embedded Design and High-Speed Interconnect
Start: 2019-10-22T09:00:00+02:00
End: 2019-10-22T16:30:00+02:00
Location: Building 28C

22 October 2019

Building 28C

Europe/Berlin timezone

Overview
Timetable
Registration

Support

thomas.walter@desy.de

Welcome and Introduction

22 Oct 2019, 10:00

15m

Seminar room FLASH (Building 28C)

Seminar room FLASH

Building 28C

DESY, Hamburg

There are no materials yet.

Choose timezone

Design and Validation of Multi-Gigabit Systems - Challenges of Embedded Design and High-Speed Interconnect

Support

Presentation materials