Speaker
Mr
Emanuele Cavallaro
(IFAE)
Description
Silicon pixel detectors based on high voltage CMOS (HV-CMOS) technologies are currently being developed to investigate the possibility to install them in the upgrade of ATLAS inner tracker (ITk) for high luminosity LHC. HV-CMOS technologies can be used to produce fully monolithic sensors, where no additional front-end chip is required, or capacitively coupled devices (CCPD) where the sensor is connected to a read-out chip with non conducting glue. Both solutions are potentially radiation hard and more cost effective than the hybrid detectors currently used in the high energy physics experiments, where the sensor and the front end chip are interconnected through bump bonding.
The H35Demo chip is a large area demonstrator ASIC produced in the AMS 350 μm HV-CMOS technology (H35). This chip, that includes both monolithic and analog matrices for CCPD, has been developed to investigate the performances of the AMS H35 technology and the opportunity to install HV-CMOS devices in the ATLAS ITk.
A readout system based on a Xilinx ZC706 FPGA board has been developed at IFAE to configure and read out the monolithic matrices. The first beam test of the monolithic matrices of an H35Demo chip has been performed in November 2016 in the CERN SPS H8 beam line
with the UniGe FE-I4 telescope. The technical challenges and the results of this first beam test will be presented.
Primary author
Mr
Emanuele Cavallaro
(IFAE)
