2nd PUNCH4NFDI TA5 Workshop on Machine Learning and Data Processing on FPGAs

Name: 2nd PUNCH4NFDI TA5 Workshop on Machine Learning and Data Processing on FPGAs
Start: 2024-09-18T13:45:00+02:00
End: 2024-09-19T13:00:00+02:00
Location: TU Dresden

18–19 Sept 2024

TU Dresden

Europe/Berlin timezone

Overview
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Contact

arno.straessner@tu-dresden.de
johann_christoph.voigt@tu-dresden.de

IPbus for FPGA slow control

19 Sept 2024, 11:30

20m

REC B214 (TU Dresden)

REC B214

TU Dresden

Technische Universität Dresden, Physics Building (Recknagelbau) Zellescher Weg 16, 01069 Dresden

Session 4

Rainer Hentges (TU Dresden)

ipbus_for_slow_control.pdf

2nd PUNCH4NFDI TA5 Workshop on Machine Learning and Data Processing on FPGAs

Contact

IPbus for FPGA slow control

REC B214

TU Dresden

Speaker

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2nd PUNCH4NFDI TA5 Workshop on Machine Learning and Data Processing on FPGAs

Contact

Speaker

Presentation materials