Preworkshop "Versal™ Adaptive SoC Architecture and Design Flow"
The flexibility and connectivity of traditional FPGAs has further expanded since the advent of AMD Versal™ Adaptive SoC Family. While the addition of CPU clusters allowed for custom specific compute acceleration already earlier, the feature set added native vector processing with the Versal™ AI Engines. We will walk through the Versal architecture and show the principles of kernel generation and system level integration.
These insights into the Versal™ design flow helps to efficiently deploy these heterogenous devices.
The Preworkshop will take place on Monday, 1 December, 2025 in the FLASH Meeting room (bulding 28c, 2nd floor).
Agenda
| Start | End | ||
| 09:00 a.m. | 10:30 a.m. | Session 1 | |
| 10:30 a.m. | 11:00 a.m. | Coffee break | |
| 11 a.m. | 12:30 p.m | Session 2 | |
| 12:30 p.m | 01:30 p.m. | Lunch break | in the DESY Canteen (15 min walk, building 9) on self-pay basis |
| 01:30 p.m. | 03:00 p.m. | Session 4 | |
| 03:00 p.m. | 03:30 p.m. | Coffee break | |
| 03:30 p.m. | 05:00 p.m. | Session 5 |
Session 1:
- Versal Adaptive SoC Technology Overview
- Architecture
- Design Tool Flow (Hardware)
- Programmable Logic
- NoC
Session 2:
- Development with Versal specific IP
- Memory
- Processing System and Embedded Design Flow Overview
- Boot and Configuration
- Extensible Embedded Platform Concepts
- Hardware, IP and Platform Development
Session 3:
- Brief recap of Versal Architecture
- Device Family on Block Level
- Vivado and Vitis Flow for Versal
- Embedded System Software Support
- Versal Software Stack
- SMP and AMP: Multicore software architecture and heterogenous designs
Session 4:
- AI Engines
- Architecture Overview
- AI Engine Programming: Kernels and Graphs
- System Integration Approaches
- System Design Flow
- Versal System Level Design Support
- Outlook: Vitis Libraries
