Lab Exercise (ISE design flow)

14 Mar 2012, 11:10
1h 20m
Konferenzraum I (Physikalisches Institut)

Konferenzraum I

Physikalisches Institut

Speaker

Victor Andrei (University of Heidelberg)

Description

Introduction to Xilinx Design Tools, Design of digital modules with Verilog, e.g. simple logical unit, shift registers edge detection, up/down counter, clock dividers, multiplexers etc.

Presentation materials