26–30 Jul 2021
Zoom
Europe/Berlin timezone

Electronic integration and commissioning of the New Small Wheel small-strip Thin Gap Chambers

Not scheduled
20m
Zoom

Zoom

Poster Detector R&D and Data Handling T12: Detector R&D and Data Handling

Speakers

Xinmeng Ye (Hefei) Xinmeng Ye (University of Science and Technology of China (CN)/University of Michigan (US))

Description

To enhance the Level-1 muon trigger selectivity and maintain good muon tracking capability under future HL-LHC runs with an instantaneous luminosity of 5-7ⅹ10$^{34}$cm$^{-2}s^{-1}$, the ATLAS experiment plans to replace the present innermost station of Muon Spectrometer in the forward region, Small Wheels, with the New Small Wheel (NSW) detector system during its Phase-Ⅰ upgrade. The NSW features two novel gaseous detector technologies, Micro Mesh Gaseous Structures (MM) and small-strip Thin Gap Chambers (sTGC). The sTGC is the primary trigger detector for the NSW, which utilizes three different types of readout electrode: pads, strips and wires. It is expected to provide segment measurements with 1 mrad accuracy for Level-1 triggering as well as high precision offline tracking under background rate up to 20kH/cm$^2$.
The sTGC electronics system employs more than 1.5k Front-end Boards populated with radiation-tolerant ASICs (Application Specific Integrated Circuit), as well as additional FPGA-based custom-made electronics cards to deal with ~400K readout channels. Complex high-speed interconnections among ASICs and electronics cards are designed to simultaneously handle a large volume of trigger and readout data from two separate data paths. The Level-1 readout up to 1 MHz is accomplished via the Front-End Link Interface eXchange (FELIX) system through the optical GBT (GigaBit Transceiver) links. The track segment reconstruction for Level-1 trigger is achieved with custom-made trigger processors hosted by an ATCA-based system.
The sTGC detector system is currently under integration and commissioning at CERN. The validation of connectivity among ~14k readout ASICs and high-speed (up to 4.8 Gbps) links, the calibration of numerous clock phases, channel threshold for optimum detector timing and operation, and the essentiality to address sensitive noise issues due to the large capacitance from sTGC pads, all pose major challenges for the final commissioning. In this presentation we will show the status and progress on the sTGC electronics integration and commissioning, the experiences gained from the establishment of integration procedures and quality control. Performance and validation of the assembled detector system will also be presented.

First author Sandra Leone
Email sandra.leone@cern.ch
Collaboration / Activity ATLAS Collaboration

Primary author

Presentation materials