3rd International Summer School on INtelligent Signal Processing for FrontIEr Research and Industry

A Pattern Recognition Mezzanine Based on Associative Memory FPGA Technology for L1 Track Triggering at HL-LHC

25 Sept 2015, 14:00

5m

SR4 2nd Floor (Hamburg)

SPECIAL POSTER SESSION

Speaker

Giacomo FEDI (INFN-Pisa, Pisa, IT)

Presentation materials

Image

image19.jpeg

Slides

PosterHamburg_v1.pdf