5th MicroTCA Workshop for Industry and Research

5 Dec 2016, 14:00 → 8 Dec 2016, 18:30 Europe/Berlin

CFEL (DESY)

Holger Schlarb (DESY), Kay Rehlich (DESY)

The 5th MicroTCA workshop for industry and research will take place from 7th to 8th December 2016 at DESY in Hamburg, Germany. DESY invites you to participate in this workshop.

The registration fee is 180 € per person including coffee and lunch breaks, DESY tour, workshop dinner and workshop materials.

Monday 5 December

14:00 → 17:00 Integration Workshop

Tuesday 6 December

10:00 → 13:00 Integration Workshop

14:30 → 17:30 Tutorial

14:30 MicroTCA.4 Tutorial Basics

Speaker: Mr Ralf Waldt (Schroff GmbH)

15:15 MTCA - Hardware Platform Management Systems Basics Tutorial

High Reliability, Availability and Serviceability (RAS) are among the most desirable features of control systems in modern High-Energy Physics (HEPs) and other big-scale scientific experiments. One of the recent developments that have influenced this field was the emergence of the xTCA standards (Advanced and Micro-Telecommunications Computing Architecture). The standards developed for telecommunication industry have been successfully applied in other domains such as accelerator control systems. The Intelligent Platform Management Interface (IPMI) with PICMG extension was applied in xTCA to enhance the availability of the system and simplify hardware diagnostics. The IPMI standard was initially developed to manage computer systems and monitor its operation. In case of xTCA, it provides useful features for shelf management, monitoring of crucial parameters, like: temperature, voltages, supply currents and fan speed. The system manages power, cooling and interconnect resource in the shelf via e-keying mechanism. The tutorial introduces the basics of hardware platform management in MTCA systems. The presentation provides information concerning IPMI basics with PICMG extension and hardware required for shelf management. Finally, the example implementation of Management Controller for Advanced Mezzanine Card (MMC) and Rear Transition Module (RMC) will be presented.

Speaker: Dr Dariusz Makowski (Lodz University of Technology, DMCS)

16:00 Tutorial MTCA.4 in Real Life

In this session hardware and software tools for MicroTCA.4 are presented, which reduce the time to bring up a MicroTCA.4 system with minimal risk. The presentation integrates a life demo which shows typical situations, how to quickly identify issues and how to solve them. The attendees learn how the key differences of the MicroTCA standard compared to other open standards make the installation and maintenance of systems in the lab and remotely in the field easier and faster.

Speaker: Mr Vollrath Dirksen (N.A.T. GmbH)

16:45 High Performance Measurement Application in MicroTCA.4

Data acquisition systems using open platform standards compared to proprietary systems offers a high modularity and the usage of a variety of different boards from various vendors. Especially the new standard MicroTCA.4 offers the benefit of combining high-speed digital data processing AMC boards together with high precision analog signal conditioning RTM boards. To achieve ultimate analog performance it requires carefully design of AMC and RTM boards, and good understanding of the electromagnetic compatibility (EMC) to maintain the required signal-integrity in a modular system. In this tutorial we show high precision applications far below -80dB using different grounding configurations. Particularly AMC and RTM ac-coupled differential signal transmission via Zone 3 for the detection and regulation of high frequency cavity fields on the fs-level and broadband dc-coupled signal conditioning on AMCs or RTMs. To achieve this we will address the following items: 1 Overview and Motivation 2 High Performance Applications in MicroTCA.4 systems 2.1 (AMC / RTM) - IF Detection for Cavity Field Regulation 2.2 (eRTMs) - Low Jitter RF and Clock Distribution 2.3 (AMC/RTM) - Broadband baseband Detection 3 EMC Zone Concepts 3.1 EMC Zones 3.2 Ground System Topologies 3.3 Interfacing Zones / Systems 3.4 Ground Loops and Breaking Methods 4 Grounding in MicroTCA.4 4.1 Grounding Configurations 4.2 Distortion coupling mechanism 4.3 Crate Ground Modelling 4.4 Measuring Ground Distortions 4.5 EMC Optimization 4.6 EMC Debugging 4.7 System Partitioning

Speaker: Dr Frank Ludwig (DESY)

Slides MTCA4_WS2016_FLudwig_final_short2.pdf

Wednesday 7 December

09:00 → 09:15 Welcome

09:15 → 09:30 Introduction

Speaker: Dr Holger Schlarb (DESY)

Slides Schlarb-_Introduction_5th_MTCAWS.idxx.pptx

09:30 → 10:30 Session 1

Convener: Raymond Larsen (SLAC)

09:30 The Large Scale MicroTCA System of the European XFEL

The European XFEL is a 3.3 km long X-Ray Free Electron Laser that is currently in the commissioning phase. The accelerator can produce up to 27 000 bunches per second. These bunches are distributed to three undulators. A flexible and independent operation of the beam lines is provided by a MicroTCA based timing system and machine protection system. All fast subsystems to readout and control the RF, the beam, and the interlocks are implemented in about 200 MicroTCA crates. The talk will give an overview of the synchronization of the facility, the protection, the diagnostics and feedback systems that are based on MIcroTCA.4.

Speaker: Kay Rehlich (DESY)

Slides Kay_Rehlich_-_The_large_scale_MicorTCA_System_of_the_European_XFEL.pptx

09:45 MicroTCA systems at ESS

The ESS has adopted the MicroTCA.4 platform for the high speed FPGA-based applications because it is one of the most promising and innovative standards for high-speed data acquisition available for accelerator controls. Some different types of MicroTCA base systems will be selected to be deployed in the facility to provide the infrastructure needed for the different systems. A few COTS AMC boards are currently being used for the ESS designs and for those systems that require an early commissioning. Some other AMCs based on the Xilinx Ultrascale FPGA families, are currently being designed and will be evaluated to define which will become the ESS standard solutions. These boards are designed to satisfy all the demanding applications in terms of data processing and interfaces throughput of the ESS high speed data acquisition systems. An overview about the ESS MicroTCA.4 platforms will be presented in this work as well as the ESS experience in collaborating with the MicroTCA.4 industry on the design and evaluation of the applications based on the standard.

Speaker: Mr Simone Farina (European Spallation Source ERIC)

Slides Simone_Farina_-_MicroTCA_systems_at_ESS.pptx

10:00 Development Activities of MicroTCA-based Systems at the SPring-8 Accelerator Complex

We are planning to change the LLRF system of the SPring-8 storage ring from the current analog-circuit-based system into a modern digital one. We started the development of a MTCA.4-based system, as it is one of the best candidates for a new standard electronics platform at SPring-8. A prototype of the LLRF system was built, consisting of commercial MTCA.4 modules, such as AMCs (SIS8300L2, Struck), a down convertor and vector modulator RTM (DWC8VM1, Struck), and so on. A feedback control function was implemented onto an FPGA firmware on the AMC module and sequence control and data acquisition are running on the CPU module with the Message And Database Oriented Control Architecture (MADOCA) control framework used at SPring-8. The prototype was installed into the high power rf test stand at the SPring-8 storage ring and the basic performance has been evaluated. We are developing a new digitizer AMC having high-speed (370 MSPS and 700 MHz bandwidth) and high-precision (16 bits) ADCs for an under-sampling rf detection scheme and it is concurrent with the test of commercial digitizers and down-converters. After the performance test of the new digitizer, the new LLRF system with the under-sampling scheme will be installed to one of the four rf stations of the storage ring next year. In addition to the LLRF system, we are developing other MTCA.4-based systems, such as a beam position monitor system and the timing synchronization system between the SACLA linac and the SPring-8 storage ring.

Speaker: Dr takashi ohshima (RIKEN)

Slides Ohshima_-_Development_Activities_of_MicroTCA-based_Systems_at_the_SPring-8_Accelerator_Complex.pptx

10:15 Applications of MTCA in SuperKEKB and KEK Facilities

History and activities of MicroTCA at KEK facilities will be reviewed and features of low-level RF control system for SuperKEKB will be mainly presented. SuperKEKB is a new upgrade project, which is aiming at 40-times higher luminosity than the KEKB, accordingly it requires much lower-emittance and higher-current beam storage. Accuracy and flexibility in accelerating field control are very essential for storage of high-current and high-quality beam without instability. Therefore, new low level RF (LLRF) control system, which is based on MTCA-platformed FPGAs (MTCA.0 standard), was developed for the SuperKEKB, and the good performance was demonstrated. The first commissioning of SuperKEKB (Phase-1) was accomplished in this year, and the new LLRF control system was successfully worked for Phase-1. Besides, in order to achieve such high luminosity, a beam-position feedback control system for the collision point of SuperKEKB has been developed by using MTCA.0-standard FPGA. On the other hand, new LLRF control system with MTCA.4 standard is also under development and its performance study is progressed in STF, which is the test facility at KEK for ILC.

Speaker: Dr Tetsuya Kobayashi (KEK)

Slides MTCA2016-KEK_Kobayashi.pdf

10:30 → 11:00 Coffee Break & Posters

11:00 → 12:30 Session 2

Convener: Mr Dietmar Mann (Schroff GmbH)

11:00 Image Processing in Banknote Printing Applications, Technology and Trends

Over the last decades, quality systems have become increasingly important in banknote printing applications. Most of these systems use high resolution RGB or multispectral line scan cameras in “inline” and “offline” production process generating high data rates. New MicroTCA-based developments with a heterogeneous computing approach address this challenge. This keynote will introduce the MicroTCA developments at KBA as follows: • KBA, a short introduction. • Visible multispectral banknote security features, an overview. • Quality systems in banknote printing applications were established in the early 1990s. Machine real time was necessary for a successful approach. Advanced banknote printing machines at that time were running up to 10.000 sheets/hour, that means 360ms for image processing of a CCIR 756x581 Pixel 8Bit monochrome image (i.e. Sony XC77-RR-CE). This was too fast for a single processor approach like intel i486, but not too fast for customized hardware or dedicated image processing boards (i.e. Datacube Inc.). VMEbus-based systems were state of the art technology for more than one decade. With the arrival of advanced high resolution RGB or multispectral line scan cameras we had to address a bandwidth gap for standard VMEbus systems, and anew approach had to be found. • MicroTCA as “low cost” high bandwidth system standard for industrial applications. • Customizing MicroTCA shelfs for image processing applications. Creating an 18 slot MicroTCA.1 shelf for cost-sensitive applications. • Heterogenous computing approach with FPGA-based image processing boards and off-the-shelf CPU AMCs using real time operating systems, Windows Embedded and AM915 as end point device. • Introducing 10GE (Vision) as a new camera interface in industrial applications with long distance “copper” capabilities on Cat6a/Cat7 cable. • Future trends: sensor fusion.

Speaker: Carsten Diederichs (KBA-NotaSys AG & Co. KG)

Slides Carsten_Diederichs_-_Image_Processing_in_Banknote_Printing_Applications.pptx

11:30 MicroTCA at FAIR

In view of the upcoming Facility for Antiproton and Ion Research (FAIR) at Darmstadt several strategies were evaluated to provide high reliable and high performance data acquisition systems for beam instrumentation applications such as beam loss, beam position and intensity measurements. MicroTCA was chosen to be one out of three supported form factors for those high data rate applications. Besides a brief status of the FAIR project an overview of MicroTCA applications at GSI and FAIR will be presented.

Speaker: Mr Tobias Hoffmann (Helmholtzzentrum für Schwerionenforschung GSI GmbH)

Slides S2_Hoffmann_MTCA_at_FAIR.pptx

11:45 xTCA relative development at IHEP Beijing

As a founding member of "xTCA for Physics", IHEP has long been in the research and development of electronics in ATCA/MTCA/AMC framework. The presentation will cover some of the developments with some applications, like in PANDA, Belle II and CMS experiment, as examples. Some design details and test results will be given. Also some design ideas of current design for future experiment will also described.

Speaker: Prof. Zhen-An Liu (IHEP Beijing)

12:00 LLRF system installation for the European XFEL

This contribution presents an overview of the complete low level radio frequency system (LLRF) installation in the European x-ray free electron laser (E-XFEL). The focus is on the MicroTCA.4-based LLRF system architecture, testing and preliminary results. Some performance results of the commissioned XFEL injector will also be presented.

Speaker: Julien Branlard (DESY)

Slides 2016_12_07_-_J.Branlard_-_MicroTCA_LLRF_system_installation_for_the_XFEL.pptx llrfInstallation.pdf

12:15 LLRF system for the European Spallation Source

The LLRF system of the ESS linear accelerator will be implemented in MTCA.4. Today there is multiple LLRF units used at different test stands, and in the near future this will scale up as more test stands and development efforts across Europe comes online. The distributed nature of the ESS project is here a challenge, but also an opportunity to build upon the strengths of using a standard such as MTCA.4. The LLRF system will be a combination of COTS parts and new parts, developed by different partners within the project.

Speaker: Dr J Johansson Anders (European Spallation Source, Lund University)

12:30 → 13:30 DESY tour 2

12:30 → 14:00 Lunch

14:00 → 15:30 Session 3

14:00 MicroTCA Hardware Standards and Software Guidelines for Physics and General Applications: A Progress Overview

Instrumentation standards for Physics applications began in Europe in the late 1950s and in the mid- 1960s a European-US collaboration produced the first widely accepted standard called NIM (Nuclear Instrument module), a simple packaging and signal standard for analog and fast digital logic that is still in use today. This was followed by three more increasingly powerful standards each enabled by the amazing growth of the electronics integrated circuit, microprocessor, firmware and multi-Gigahertz serial communications technologies which make up today’s world of the petabyte data collection and mining for not just experiments but medical imaging diagnostics across all of society, the massive experiments of the LHC, XFEL, ESSB and many others, and hopefully soon the long-awaited ILC in Kitakami Japan. Each of these scientific programs drives many new complex technologies which impact the need for new smarter standards. The lab –industry collaboration known as PICMG xTCA for Physics has reached the latest milestone in lab standards called MTCA.4 and MTCA.4.1, a complete hardware-software system integrated with Intelligent Platform Management and a number of hardware Classes and software Guidelines and use cases to increase the interoperability of new applications modules developed by the growing lab-industry collaboration.

Speaker: Raymond Larsen (SLAC)

Slides Ray_Larsen_-_MicroTCA_Hardware_Standards_and_software_Guidelines.pdf

14:15 Standard Hardware API for MicroTCA.4 Systems

The adoption by experimental physics community of the Advanced Telecommunication Computing Architecture (ATCA), maintained by the PCI Industrial Computer Manufacturers Group (PICMG), in recent years will lead to the development of a multitude of embedded instrumentation and machine control applications. Having a set of standards and definitions will encourage hardware and software component interoperability and portability among the various scientific centers. This motivation has lead a MTCA.4 committee, formed to extend the ATCA family of standards, to define the Standard Hardware Application Programming Interface (SHAPI) guideline. Developed, but not limited, for MicroTCA.4 systems, SHAPI provides a standardized and portable way for software applications to interact with physical hardware devices. It defines a structural and methodological approach to device access and interrupt handling while not restricting the physical communications channels and the address mechanisms by which software accesses such channels. In this presentation, we describe the main SHAPI definitions and advantageous.

Speaker: Mr Bruno Fernandes (European XFEL)

Slides Bruno_Fernandes_-_Standard_Hardware_API_for_MicroTCA.4_Systems.pptx

14:30 Benefits and Management of a second backplane in MTCA.4 systems (upcoming MTCA.4.1 standard)

Driven by the need to merge an analogue (RF) and a digital system into one single chassis DESY invented another backplane next to the AMC backplane for their MicroTCA.4 systems. In strong cooperation with other institutes and industrial partners this idea was extended and turned into a draft standard, submitted to PICMG as MTCA.4.1. This presentation will show how the original idea of a second backplane got extended by additional features and new components, such as Rear Power Modules (RPMs), extended RTMs (eRTMs) and management. Also several application examples and use cases for MicroTCA.4.1 are given, i.e. LLRF concept for RTM backplane for sensitive analogue signals, additional power to µRTMs and eRTMs, interconnecting µRTMs and eRTMs industrial concepts of RTM backplane for SDR and eNodeB

Speaker: Mr Heiko Körte (N.A.T. GmbH)

Slides Heiko_Koerte_-_Benefits_and_Management_of_a_second_backplane_in_MTCA.4_systems.pdf

14:45 MicroTCA platform enhancements

MicroTCA is used across industry and research, as the flexibility provided by the standards is used to expand platform capabilities for new applications. This paper presents enhancements in power and connectivity, in the context of user applications that stretch the platform capability to the limit.

Speaker: Mr Ian Shearer (VadaTech Ltd)

Slides Ian_Shearer_-_MicroTCA_Platform_Enhancements.pdf

15:00 Pentair MTCA.4 system product portfolio

Different application demand different crate solutions. Therefore Pentair has, over the last years, developed a wide range of different crates. This presentation introduces the Schroff MTCA.4 crates and its specifications.

Speaker: Mr Christian Ganninger (Pentair Technical Solutions GmbH)

Slides Ganninger_-_Pentair_MTCA.4_system_product_portfolio.pptx

15:15 Intelligent Data Acquisition Board Including Epics Support

IOxOS Technologies unveils the IFC_1410 Single Board Computer AMC module, the cornerstone of its new MTCA.4 product line of AMCs and µRTMs combining latest T-Series NXP processors and high-end Kintex UltraScale FPGAs from Xilinx with a comprehensive FPGA Design Kit and a set of high-performance FMC modules. The high computing performance per watt of the QorIQ platform series and the powerful versatility and capacity of these cutting-edge FPGAs, together with their long term availability, make this platform ideal for the implementation of sophisticated FPGA-driven applications targeting precision instrumentation and state-of-the-art accelerator control systems.

Speaker: Iván García-Alfonso (IOxOS)

Slides Ivan_Garcia_-_Intelligent_Data_Acquisition_Board_including_epics_support.pdf

15:30 → 16:00 Coffee Break

16:00 → 17:15 Session 4

16:00 RackPak/M5-1, the next step MTCA.4 chassis

The talk will highlight the new MTCA.4 chassis, which was developed in a joint effort between NAT, Pentair and powerBridge. This new chassis is the next evolution step towards optimal utilization of feature sets provided in MTCA.4. It will highlight to differences to existing chassis as well give an in detail looks to the topology and unique new functions and features.

Speaker: Mr Thomas Holzapfel (industrie partner)

Slides pBC_2016-12_powerBrigde_5._MTCA_workshop.pdf

16:15 High Bandwidth Data Acquisition (HBDQ) MTCA.4.1 Platform

This presentation shows how the latest technology enhancements, new upcoming sub-standard MTCA.4.1 and more backplane interconnection create a new performance level of data acquisition. NATIVE-R2 HBDQ platform doubles the bandwidth to each IO-Card and CPU card in its 6 AMC slots and quadruples the bandwidth to the aggregation processing nodes inside and outside the chassis. The NATIVE-R2-HBDQ combines a 2U MTCA.4.1 chassis offering 8 PCIexpress lanes to each AMC slot with the NAT-MCH-PHYS80 offering 80 PCIexpress lanes, where two times 16 PCIexpress lanes (128 Gb/s) are routed to high performance aggregation and processing CPU inside and/or outside the chassis. It comes with the infrastructure for Timing Synchronisation solution based on NAMC-psTimer ( compatible to x2-Timer) and/or White-Rabbit Clock module. NATIVE-R2 HBDQ comes with pre-installed Linux operating system and driver and application software for plugged in timing and synchronisation hardware and for high performance DAQ boards. Cascading the NATIVE-R2 HBDQ solution provides in an 8U frame space for 24 AMC (each with a bandwidth of 64 GT/s) and 24 µRTM slots.

Speaker: Mr Vollrath Dirksen (N.A.T. GmbH)

Slides Vollrath_Dirksen_-_High_Bandwidth_Data_Acquisition_(HBDQ)_MTCA.4.1_Platform_-_Session_4.pdf

16:30 New SP Devices MTCA Digitizers designed for fast electronics applications in Physics

- SP Devices introduces new ultra-fast digitizing solutions with embedded processing in MTCA form factor for demanding applications such as high speed diagnostics in physics. - SP Devices continues to improve current products offering by developping new clock and trigger synchronisation capabilities over the MTCA backplane.

Speaker: Mr Laurent Weber (Signal Processing Devices AB)

Slides L.Weber_-_New_SP_Devices_MicorTCA_Digitizers_designed_for_fast_electronics_applications_in_Physics.pptx

16:45 Kintex Ultrascale based MTCA digitizer cards, the SIS8300-KU and beyond

The user demand to develop custom digitizer firmware for the SIS8300 family with the current Xilinx Vivado toolchain required a new post Virtex 6 design. First prototypes of the Kintex Ultrascale based SIS8300-KU 125 MSPS 16-bit MTCA.4 Digitizer came out of stuffing mid of November. Design parameters and first results of the new card will be presented. Test results from (multi)-GSPS 14/16-bit digitizer chip evaluation cards will be shown and possible upcoming JESD204 designs will be addressed in the outlook.

Speaker: Dr Matthias Kirsch (Struck Innovative Systeme GmbH)

Slides Matthias_Kirsch_-_Kintex_Ultrascale_based_MTCA_digitizer_cards.pdf

17:00 "MicroTCA Technology Lab" at DESY: Status Update and Outlook

As of October 2016, DESY has started to establish a new interface towards industry for all MicroTCA activities: the MicroTCA Technology Lab. Firmly attached to MSK (Machine Controls Group) and closely collaborating with TT (Technology Transfer), its primary mission is to reach well beyond the realm of particle accelerators and provide solutions for MicroTCA applications in other industries that face similar challenges. Funded jointly by the Helmholtz Association, DESY and industry, it will resume a range of activities and that have been started during the Helmholtz Validation Fund project HVF-0016 "MicroTCA.4 for Industry" to provide extensive support to developers, manufacturers and users in all facets of MicroTCA design, development, test and debugging. The MicroTCA Technology Lab will license the latest DESY designs, provide test & measurement services, serve as a hub for advanced development projects and develop custom MicroTCA designs for specific applications.

Speaker: Dr Thomas Walter (DESY)

Slides Thomas_Walter_-_MicroTCA_Technology_Lab_at_DESY.pptx

19:00 → 22:30 Workshop Dinner

Thursday 8 December

09:00 → 10:15 Session 5

Convener: Mr Tobias Hoffmann (Helmholtzzentrum für Schwerionenforschung GSI GmbH)

09:00 How to build your own 3GHz spectrum analyzer and achieve -155dBm/Hz noise floor

Signal spectrum analysis is a key function in scientific research. Analog Devices offers a reference design for a 3GHz spectrum analyzer with -155dBm/Hz noise floor, built on all Analog Devices parts. New parts and clever design techniques help to shift the limits of physics.

Speaker: Mr Kai Rohm (Analog Devices - US Manufacturer of high end analog and RF parts)

Slides Kai_Rohm_-_Inside_the_all_ADI_3_GHz_Signal_Analyzer.pdf

09:30 MTCA.4 Usage in the Femtosecond-synchronization System at European XFEL

The optical synchronization system at the European XFEL serves as femtosecond-stable reference throughout the 3.5 km long facility. Its signal is essential for the pump-probe experiments, first by enabling the LLRF system to stabilize the the electron bunch arrival time and thereby the FEL X-ray pulse timing, and second by synchronizing the experimental laser to fs precision. Most of the electronic hardware is realized in various MTCA.4 AMC-, RTM-, and FMC-Modules, most of them specially designed for this aplication. Several digital control feedback loops are implemented on FPGAs for the laser synchronization, the fiber link stabilization, and the 32 different end-stations. This talk will give a short introduction on the system and explain the involved hardware and software components.

Speaker: Mr Matthias Felber (DESY)

Slides 16'12_Felber_MTCA-WS.pdf

09:45 Beam-based Arrival Time Feedback at FLASH

The free-electron laser FLASH with its up to 400us long bunch trains and high bunch repetition rates allows for applying an intra-train feedback system for an arrival time jitter reduction which is mandatory for many of today's pump-probe experiments. Such a fast feedback system is based on superimposing the RF field information with beam-based measurements in an optimized Low-Level RF (LLRF) controller. The principle of operation had already been shown on a former electronics platform. Now, we have proven its functionality with the new MicroTCA.4 based system. The LLRF frontend receives the beam-based information from the Bunch Arrival Time Monitor (BAM) via an optical Multi-Gigabit link. The BAM application has been implemented on a Virtex-5 FPGA carrier utilising a specialised double-width FPGA Mezzanine Card (FMC), which incorporates following main features: 3 optical channel inputs (data and clock) with 800MHz InGaAs photodiodes followed by 2GHz current-feedback amplifiers, a clock generator module with integrated 2.8GHz voltage control oscillator (VCO), 4 ADCs for dual channel interleaved sampling at 16 bit with up to 250 MSPS. Here, we present the MicroTCA.4 based frontend of the BAM and its application for the fast beam-based feedback system; the recent measurements have shown a bunch timing jitter reduction to below 20fs with simultaneous flattening of the timing slope across the bunch train, which was achieved during 24h long runs of a photon user's experiment.

Speaker: Mrs Marie Kristin Czwalinna (DESY)

Slides Marie_Kristin_Czwalinna_-_Beam-based_Arrival_Time_Feedback_at_FLASH.pdf

10:00 MicroTCA.4 based LLRF System for the RFQ of C-ADS Injector I

The C-ADS Injector I consists of one RFQ, two normal conducting bunchers and 14 superconducting cavities. The 325MHz RF frequency RFQ runs in CW mode and an inter-electrode voltage of 55kV is needed to accelerate the 3mA~10mA proton beam up to 3.2MeV. The RFQ is powered by a CW klystron and the RF power in the RFQ is up to 280kW. The high power conditioning of RFQ and beam commissioning of the Injector I are accomplished by the LLRF system based on the MicroTCA.4 standard hardware. The LLRF system supports both CW and duty-adjustable pulsed operation modes for the high power source and the RFQ. The firmware of the FPGA controller, the EPICS IOC and operator interface software are described. The performance of automatic conditioning/operation script programm is illustrated.

Speaker: Dr Xinpeng Ma (Institute of High Energy Physics, Chinese Academy of Sciences)

10:15 → 11:00 Coffee

11:00 → 12:15 Session 6

11:00 A build system for DAMC-FMC25 Board Support Package

In the development of custom applications based on the DAMC-FMC25 Board Support Package an advanced build system is used to ensure high quality of the application as well as traceability of the source code and possibility to reproduce the build. The build system is composed of three parts: a tcl script which rebuilds the entire project directly from the source code from version control, a Python script which runs all unit tests to check the inconsistencies between design and implementation, and a Doxygen (Doxverilog) configuration file which automatically creates low-level documentation from the comments in the source code. The use of automated tests dictates a modular design, which simplifies migration of FPGA modules between FPGA families. Build system integrates AXI Bus Functional Models which can be used to exercise and collect data from the Module Under Test. A comparison of our build system with hdlmake will be given and some examples of migration from Virtex-5 series FPGA to Kintex UltraScale series FPGA will also be presented.

Speaker: Mr Jan Marjanovic (CAEN ELS d.o.o.)

Slides mtcaws_2016_marjanovic.pdf

11:15 How to make sure that your crate works like expected

Cooling and backplane data transfer are two very critical topics for a MTCA.4 crate. 40G or 100G backplane transfer are essential today and this leads to dramatically increasing power per board. The crates have to be built in a way to support this. But how to make sure that the crate works like expected? This presentation is providing some insights of how Pentair is testing its crates.

Speaker: Mr Christian Ganninger (Pentair Technical Solutions GmbH)

Slides Christian_Ganninger_-_How_to_make_sure_that_your_crate_works_like_expected.pptx

11:30 Advances using Intel processor technology

Intel processor based AdvancedMC modules are mainly used for management and control purposes. These boards possess a number of additional capabilities that can provide useful performance gains and enable the Intel based resources to be used for some data processing. In particular, the presentation will show what can be achieved using virtualisation and GPU acceleration. The presentation will also cover a general roundup of other features that may be interesting for some applications

Speaker: Mr Nigel Forrester (Concurrent Technologies)

Slides CCT_Advances_using_Intel_Technology.pdf

11:45 A Low-Cost MicroTCA Crate for use in Low-End Machine Control Systems

This talk will present our current ongoing development of a low-cost MicroTCA system, for the control of “low-end” accelerator components (such as magnets, vacuum, cryogenics etc.). The system utilizes MicroTCA’s key concepts and specifications, but has a modified backplane and power-subsystem. It is comprised of one CPU/FPGA card, and several, so-called, “Front-End” cards. The modified backplane enables the CPU/FPGA card, to have direct Point-to-Point connections to the Front-End cards, which act as an Interface-Bridge between the CPU/FPGA Card and the controlled components (Magnets PS, for example). This enables one CPU card to control several low-end systems.

Speaker: Mr Ofir Shefer Shalev (DESY Hamburg)

Slides Ofir_Shefer_Shalev_-_A_Low-Cost_MicroTCA_Crate_for_use_in_Low-End_Machine_Control_Systems.pptx

12:00 High Voltage Power Module Pluggable to NAT RTM Power Supply Carrier

In the paper we want to present High Voltage Power Module (HVPM) pluggable to Micro Telecommunication Computing Architecture generation four (MTCA.4) based Rear Transition Module (RTM) Power Supply Carrier (PSC) and its possible applications. The idea is to have a possiblity to power supply RTM cards that demands specific voltages above 12VDC. The HVPM module is composed of high voltage dc/dc bricks and onboard diagnostics. The dc/dc power modules are designed to make up conversion from 48VDC input voltage to demand +/-100VDC output voltage. The 48VDC input voltage is generated by the PSC using 220VAC input voltage. The onboad diagnostics allow monitoring temperature of the modules, output power, voltage as well as current consumption when operated under load condition. The HVPM is pluggable to RTM PSC and communicates with the carrier using standard i2c bus communication protocol. The HVPM maintanance can be obtained using debug serial console available directly from the carrier or using the MicroTCA Carrier Hub (MCH) installed on the front of the standard MTCA.4 crate.

Speaker: Dr Konrad Przygoda (DESY)

Slides MTCA_HVPM_KP.pdf MTCA_HVPM_KP.pptx

12:15 → 13:15 DESY Tour 3

12:15 → 13:45 Lunch

13:45 → 15:15 Session 7

Convener: Mr Ian Shearer (VadaTech Ltd)

13:45 Error Prevention for µ-Components on Circuit Boards

Components with flat termination on package bottom side - so called Bottom Termination Components according to IPC-7093 - are the fastest growing component family on electronic circuit boards. A terminal pitch of 400µm meanwhile is standard for new packages and due to market requirements electronic component packages continously become smaller and smaller. Due to many package variations and sometimes extremely area differences between thermal pads and the sum of peripheral pads fundamental knowledge is required for appropriate land dimensioning. The circuit board designer must know about processing risks of different component packages to design error free and save to manufacture circuit boards. As the thickness of the smallest components meanwhile is in the range of 100µm and solder joints thickness very often is below 50µm, circuit board topology - soldermask and silksreen becomes a critical part and can dramatically influence reliability of electronic assemblies The presentation adresses the risks of bottom terminated µ-Components and gives guidelines for dimensioning of landpattern and save processing of this package types.

Speaker: Rainer Taube

Slides Rainer_Taube_-_Failure_Prevention.pdf

14:15 Mezzanine style RTMs, optical detector example

The MTCA.4 standard uses the concept of industry-generated AMCs and user-generated RTMs to provide economies of scale (for AMCs) and flexibility (via RTMs). For users new to MTCA, the overhead of designing to the RTM standard can be daunting, so a standard RTM accepting user-designed mezzanines has been produced. This first application of this is a collaboration between the University of Oxford, VadaTech Inc. and Etalon AG. The capabilities of the resulting photodetector and signal conditioning unit is presented, together with an overview of the design concepts used.

Speakers: Prof. Armin Reichold (Oxford University), Mr Ian Shearer (VadaTech Ltd)

Slides Armin_Reichold_Ian_Shearer_-_Mezzanine_style_RTMs.pdf

14:30 High Speed Optical Line Detector for MTCA.4 Systems

Some physical phenomena can be conveniently analysed using just a single photo-element, others may require high-resolution cameras, but there is also a need for linear detectors. Such devices can offer a much higher frame rate than traditional cameras while still providing kilobytes of useful information per frame. Commercially available line cameras and sensors from leading manufacturers can only reach a frame rate of around 200 kHz. To perform valuable measurements on the DESY machines, an order of magnitude faster acquisition is required. Such a custom system working with frame rate of up to 4.5 MHz, acquiring and processing several gigabits of data per second, is described and demonstrated in the presentation.

Speaker: Mr Aleksander Mielczarek (Lodz University of Technology)

Slides Aleksander_mielczarek_-_High-speed_optical_line_detector_for_MTCA.4_systems.pdf

14:45 Application of MicroTCA in ADS Proton Linac Injector I at IHEP

The ADS Proton Linac Injector I is composed of an ion source, a low energy beam transport line, a 325MHz radio-frequency quadrupole, a medium energy beam transport line, a superconducting linac and a beam dump. The Low-level RF control system(LLRF) of the test facility adopts a hardware platform based on MicroTCA.4. We have developed the LLRF firmware and applications and now completed a preliminary commissioning and put them into operation. It is expected that the CW beam will be realized in the short future after the breakthghout 10MeV pulsed Proton beam has been achieved . This talk will talk about the application of MicroTCA in ADS Proton Linac Injector I at IHEP.

Speaker: Dr Rong Liu (Institute of High Energy Physics, Chinese Academy of Sciences(IHEP))

15:00 MicroTCA.4-based Beam Charge Measurement for XFEL and FLASH/FLASH2

A Beam Charge Measurement system with a resolution of 0.2 pC RMS was developed for XFEL and FLASH/FLASH2. In addition, the system provides beam loss detection from differential measurements over optical fibers, based on the "bunchpattern" information provided by the Timing System. This presentation will show the implementation in MicroTCA.4 with a Struck SIS8300L2D AMC, a special RTM and an analogue frontend. The connection to the Timing System will be discussed as well as the interface to the Machine Protection System (MPS). The differential beam loss detection will be explained, and our experiences from commissioning and first operation will be reported.

Speaker: Mr Matthias Werner (DESY)

Slides M_Werner_-_uTCA.4_based_Beam_Charge_Measurement.pdf

15:15 → 15:45 Coffee

15:45 → 16:45 Session 8

Convener: Mr Vollrath Dirksen (N.A.T. GmbH)

15:45 From MTCA4U to ChimeraTK: A device abstraction toolkit to facilitate the development of control applications

In 2013 the MTCA4U tool kit started as a hardware access library for PCI Express based AMCs in MicroTCA.4 crates. Due to its modular, register based interface for hardware abstraction, backends to communicate through network protocols and even to other control applications have been added, extending the use of the tool kit beyond just MicroTCA. Hence the project has been renamed to ChimeraTK (Control system and Hardware Interface with Mapped and Extensible Register-based device Abstraction Tool Kit). Written in C++, the device access library features an easy to use interface with bindings to Python, Matlab and the command line, and a graphical user interface. In addition ChimeraTK provides a "virtual lab" library which facilitates testing, and a control system adapter. This adapter layer allows to write control applications independently from the controls middleware. Like this it can be integrated into different control environments using DOOCS, EPICS or OPC-UA, for instance, without changes in the source code. With the new 'application core' library an efficient interface with compact syntax has been introduced to reduce the amount of code which has to be written. We report on the status of the development and show the latest features of the tool kit.

Speaker: Martin Killenberg (DESY)

Slides From_mtca4u_to_ChimeraTK_Killenberg161208.pdf

16:00 User Application and PCIe performance in MTCA

With increase in number of modules in a MTCA crate and client programs, and also with complication of modules and increase in number of module registers, usual register I/O access to the module plays an important role in PCIe transfer rate. In this presentation different access methods to the PCI Express endpoint and their influence on transfer rate are provided. The main attention is concentrated on interaction of the user application and device driver.

Speaker: Mr Ludwig Petrosyan (DESY)

Slides Ludwig_Petrosyan_-_MTCA_PCIe_perfomance.pdf

16:15 LINUX general purpose PCIe driver for MTCA

Micro Telecommunications Computing Architecture (MTCA) is the new generation system, which should allow more stable and reliable control of the accelerator facilities such as the FLASH, the European XFEL, the PITZ and etc. Software development for MTCA devices is among the important tasks. It is undeniable that user space software development is preferable to kernel space software development. Therefore kernel space general purpose driver based on MTCA standards was developed. In the most cases only user space software will be enough to adopt new MTCA devices. The design and the development of the general driver started in 2013 with the objective of finally creating a driver that is able to handle as many MTCA devices as possible. The following rule is always kept: if a generalization of any functionality leads to penalty in performance or increase in memory usage or too complicated code is abandoned. In the case a device is not possible to be handled by this driver due to device very specific functionality, driver stacking can be used. The driver can be parent driver for specific device driver. This means for specific device driver only specific functionalities should be implemented with less coding. The driver already has use cases. Currently some of the functionalities of this driver are included to the ‘upciedev’ driver that is very widely used in DESY Hamburg. There is a plan after tests to include more general functionalities like interrupt handling DMA access etc. The functionalities implemented so far, a comparison of different DMA schemas, and the performance analysis for some generalized functionalities also will be presented.

Speaker: Dr Davit Kalantaryan (DESY)

Slides Davit_Kalantaryan_-_linux_pcie_mtca_driver.pdf

16:30 Closeout

Speaker: Dr Holger Schlarb (DESY)

Slides 2016-12-08-close_out_HS.pptx