Advanced Techniques in LLRF control for XFEL - Collaboration Workshop

6 Aug 2012, 08:00 → 8 Aug 2012, 18:00 Europe/Berlin

Main Auditorium A1/A2 (Department of Microelectronics and Computer Science)

Frank Ludwig (DESY), Holger Schlarb (DESY), Mariusz Grecki (DESY)

Advanced Techniques in LLRF control for XFEL - Collaboration Workshop provides a chance for people involved in development of hardware and software parts of LLRF control system to present their work and discuss plans for the future. It is focused on LLRF solutions for FLASH and XFEL and will take place at the Technical University of Lodz, Poland August 6 to August 8.

Monday 6 August

09:00 → 10:15 Session 1 - LLRF Systems Overview

09:00 Welcome and Introduction to Workshop

Speaker: Prof. Andrzej NAPIERALSKI (TUL-DMCS)

09:10 Organization issues

Speaker: Mr Adam Piotrowski (Technical University of Lodz, DMCS)

09:15 LLRF System Status at CMTB & AMTF

Speakers: Julien Branlard (DESY), Wojciech Cichalewski (TUL-DMCS)

Slides S1_P1-J_Branlard-CMTB_and_AMTF_Status_Report-Lodz_2012.pptx

09:45 LLRF System status REGAE & TDS Zeuthen

Speaker: Dr Matthias Hoffmann (DESY)

Slides S1_P2-M_Hoffmann-LLRF_System_Status_at_REGAE_and_TDS-Lodz_2012.pdf

10:15 → 10:35 Coffee Break

10:35 → 12:00 Session 2 - LLRF Systems Overview

10:35 EBPM System Status at FLASH

Speaker: Uros Mavric (DESY)

Slides S2_P1-U_Mavric-EBPM_System_Status_at_FLASH-Lodz_2012.pptx

10:55 LLRF Installation for the XFEL

Speakers: Julien Branlard (DESY), Dr Krzysztof Czuba Czuba (ISE)

Slides S2_P2a-J_Branlard-LLRF_Installation_for_the_XFEL-Lodz_2012.pptx S2_P2b-K_Czuba-MO_and_RF_Distribution_Installation_for_XFEL-Lodz_2012.pdf

11:25 Main changes XFEL LLRF System & HGF Validation fond perspectives

Speaker: Dr Holger Schlarb (DESY)

Slides S2_P3-H_Schlarb-Main_changes_XFEL_LLRF_System_and_HGF_Validation_fond_perspectives-Lodz_2012.ppt

12:00 → 13:30 Lunch

13:30 → 15:10 Session 3 - LLRF uTCA Subsystems - Progress and Status

13:30 MTCA.4 Platform Compatibility & Bugfixing

Speaker: Uros Mavric (DESY)

Slides S3_P1-U_Mavric-MTCA.4_Platform_Compatibility_and_Bug_fixing-Lodz_2012.pptx

13:50 Hardware & Firmware and Functionality of XxTIMER

Speaker: Holger Kay (DESY)

Slides S3_P2-H_Kay-The_XFEL_Timing_System-Lodz_2012.ppt

14:10 KLM Status

Speaker: Mr Łukasz Butkowski (ISE)

14:30 uPS Design Status

Speaker: Dr Tomasz Jezynski (DESY)

Slides S3_P4-T_Jezynski-uPS_Design_Status-Lodz_2012.pdf

14:50 FMC25 Design and Status

Speaker: Mr Stefan Korolczuk (The Andrzej Soltan Institute for Nuclear Studies (IPJ))

Slides S3_P5-S_Korolczuk-uTCA25_Design_and_Status-Lodz_2012.pdf

15:10 → 15:30 Coffee Break

15:30 → 17:00 Working Groups

15:30 Discussion: MCH, crates and power supply compatibility problems

15:35 Discussion: Bug reporting applications and procedures

15:40 Tutorial and discussion: how to set up MTCA system from scratch

15:45 Discussion: Other problems presented during MTCA.4 Platform Compatibility & Bugfixing presentation.

Tuesday 7 August

08:30 → 10:00 Session 4 - SIS Board HW/FW/SW

08:30 Functional block diagram for SIS8300

Speaker: Mr Christian Schmidt (DESY)

Slides S4_P1-C_Schmidt-Functional_block_diagram_for_SIS8300-Lodz_2012.pdf

08:45 SIS8300L Design Status

Speaker: Dr Frank Ludwig (DESY)

Slides S4_P2-F_Ludwig-SIS8300L_Design_Status-Lodz_2012.pdf

09:10 DWC8300FR 2.1 Design Status

Speaker: Mr Dominik Sikora (ISE, Warsaw University of Technology)

Slides S4_P3-D_Sikora_P_Barmuta-Status_of_the_uDWC8300_v_2_1-Lodz_2012.pdf uDWC-18.0000_30-07-2012__report.pdf

09:35 SIS8300 Firmware Status

Speaker: Mr Wojciech Jalmuzna (DMCS)

Slides S4_P4-W_Jalmuzna-SIS8300_Firmware_Status-Lodz_2012.pdf

10:00 → 10:30 Coffee Break

10:30 → 12:00 Session 5 - uTC Board HW/FW/SW

10:30 Functional block diagram for uTC

Speaker: Mr Christian Schmidt (DESY)

Slides S5_P1-C_Schmidt-Functional_block_diagram_for_uTC-Lodz_2012.pdf

10:45 uTC (V6) specification & resource budget

Speaker: Mr Dariusz Makowski Makowski (Tech. Univ. of Lodz, DMCS)

Slides S5_P2-D_Makowski-uTC_Specification_and_Resource_Budget.pdf

11:10 uVM Design Status

Speaker: Mr Igor Rutkowski (ISE, Warsaw University of Technology)

Slides S5_P3-I_Rutkowski-MTCA_4_RTM_Vector_Modulator_Design_Status-Lodz_2012.pdf

11:35 uTC Firmware Status

Speaker: Mr Wojciech Jalmuzna (DMCS)

Slides S5_P4-W_Jalmuzna-uTC_Firmware_Status-Lodz_2012.pdf

12:00 → 13:30 Lunch

13:30 → 15:00 Working Group

13:30 Tutorial and discussion: how to use DSP elements available in FPGA

13:35 Discussion: documentation for LLRF systems

13:40 Discussion: problems with timing modules

14:00 Discussion: uTC resources and specification

15:00 → 15:30 Coffee Break

15:30 → 17:00 Session 6 - LLRF uTCA Subsystems - Progress and Status

15:30 uDS86800 + RTM Design Status

Speaker: Mr Samer Bou Habib (ISE, Warsaw University of Technology)

Slides S6_P1-S_Bou_Habib-uDS800_and_RTM_Design_Status-Lodz_2012.ppt

15:50 uRFB Design Status

Speaker: Dr Krzysztof Czuba (ISE, Warsaw University of Technology)

Slides S6_P2-K_Czuba-uRFB_Design_Status-Lodz_2012.pdf

16:10 uLOG Design Status

Speaker: Uros Mavric (DESY)

Slides S6_P3-U_Mavric-uLOG_Design_Status-Lodz_2012.pptx

16:30 ZONE 3 Classification

Speaker: Mr Dariusz Makowski Makowski (Tech. Univ. of Lodz, DMCS)

Slides S7_P4-D_Makowski-ZONE_3_Clasification.pdf

18:30 → 21:00 Workshop Dinner

Wednesday 8 August

08:00 → 09:40 Session 7 - LLRF 19"Module Subsystems - Progress and Status

08:00 TMCB 2.0 Revision Status

Speaker: Mr Jaroslaw Szewinski (Soltan Institute for Nuclear Studies)

Slides S7_P1-J_Szewinski-TMCB_2_0_Revision_Status-Lodz_2012.pdf

08:15 DCM Revision Status

Speaker: Mr Jan Piekarski (Warsaw University of Technology - Institute of Electronic Systems)

Slides S7_P2-J_Piekarski-Drift_Calibration_Module-Lodz_2012.pdf

08:30 LOGM Revision Status

Speaker: Mr Mateusz Zukocinski (Warsaw University of Technology)

Slides S7_P3-M_Zukocinski-LOGM_Status_Report-Lodz_2012.ppt

08:45 PZT Revision Status

Speaker: Mr Konrad Przygoda (TUL)

Slides S7_P4-K_Przygoda-PZT_Revision_Status-Lodz_2012.pdf

09:00 PSM Status

Speaker: Mr Daniel Kuehn (DESY)

Slides S7_P5-D_Keehn-LLRF_Rack_Power_Supplies_Status-Lodz_2012.pdf

09:10 MO Status

Speaker: Mr Lukasz Zembala (ISE, Warsaw University of Technology)

Slides S7_P6-L_Zembala-XFEL_MO_status-Lodz_2012.pdf

09:25 REFM Revision Status

Speaker: Mr Dominik Sikora (ISE, Warsaw University of Technology)

Slides S7_P7-D_Sikora-Reference_Modules_REFM-Lodz_2012_-_REFM.pdf

09:40 → 09:55 Coffee Break

09:55 → 11:30 Session 8 - DOOCS Servers and Software for LLRF System

09:55 Frontend server architecture and status

Speaker: Mr Adam Piotrowski (Technical University of Lodz, DMCS)

Slides A.Piotrowski.pdf

10:25 New Naming Convention for DOOCS Servers

Speaker: Julien Branlard (DESY)

Slides 2012_08_08_-_J.Branlard_-_Server_naming_and_DAQ_for_the_XFEL.pdf

10:45 Automation for DOOCS servers for AMTF

Speaker: Wojciech Cichalewski (TUL-DMCS)

Slides 2012-08-14T08_57_33-00.pdf

11:00 Middle layer server for loaded Q characterization

Speaker: Katarzyna Gnidzinska (DMCS/TUL)

Slides Ql_characterisation.pdf

11:10 Recent FB & calibration results at FLASH LLRF System

Speaker: Mr Sven Pfeiffer (DESY)

11:30 → 12:50 Lunch

12:50 → 13:55 Working Group

12:50 Discussion: problems with jDDD

12:55 Discussion: universal server structure – how to develop server for different system