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Advanced Techniques in LLRF control for XFEL - Collaboration Workshop

→ Europe/Berlin
Main Auditorium A1/A2 (Department of Microelectronics and Computer Science)

Main Auditorium A1/A2

Department of Microelectronics and Computer Science

ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
Frank Ludwig (DESY), Holger Schlarb (DESY), Mariusz Grecki (DESY)
Description


Advanced Techniques in LLRF control for XFEL - Collaboration Workshop provides a chance for people involved in development of hardware and software parts of LLRF control system to present their work and discuss plans for the future. It is focused on LLRF solutions for FLASH and XFEL and will take place at the Technical University of Lodz, Poland August 6 to August 8.

Participants
  • Adam Piotrowski
  • Andrzej Napieralski
  • Bin Yang
  • Christian Schmidt
  • Daniel Kühn
  • Dariusz Makowski
  • Dominik Sikora
  • Ewa Janas
  • Frank Ludwig
  • Henning Weddig
  • Holger Kay
  • Holger Schlarb
  • Ignacy Kudla
  • Igor Rutkowski
  • Jan Piekarski
  • Jan Wychowaniak
  • Jaroslaw Szewinski
  • Julien Branlard
  • Katarzyna Gnidzinska
  • Konrad Przygoda
  • Krzysztof Czuba
  • Lukasz Butkowski
  • Lukasz Zembala
  • Maciek Grzegrzółka
  • Marek Dominik
  • Mariusz Grecki
  • Mateusz Żukociński
  • Matthias Felber
  • Matthias Hoffmann
  • Paweł Barmuta
  • Paweł Gontarek
  • Paweł Prędki
  • Przemysław Kownacki
  • Samer Bou Habib
  • Stefan Korolczuk
  • Sven Pfeiffer
  • Tomasz Jezynski
  • Tomasz Kozak
  • Tomasz Pozniak
  • Uros Mavric
  • Valeri Ayvazyan
  • Wojciech Cichalewski
  • Wojciech Jalmuzna
  • Monday 6 August
    • 09:00 → 10:15
      Session 1 - LLRF Systems Overview Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 09:00
        Welcome and Introduction to Workshop 10m
        Speaker: Prof. Andrzej NAPIERALSKI (TUL-DMCS)
      • 09:10
        Organization issues 5m
        Speaker: Mr Adam Piotrowski (Technical University of Lodz, DMCS)
      • 09:15
        LLRF System Status at CMTB & AMTF 30m
        Speakers: Julien Branlard (DESY), Wojciech Cichalewski (TUL-DMCS)
        Slides
      • 09:45
        LLRF System status REGAE & TDS Zeuthen 30m
        Speaker: Dr Matthias Hoffmann (DESY)
        Slides
    • 10:15 → 10:35
      Coffee Break 20m Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
    • 10:35 → 12:00
      Session 2 - LLRF Systems Overview Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 10:35
        EBPM System Status at FLASH 20m
        Speaker: Uros Mavric (DESY)
        Slides
      • 10:55
        LLRF Installation for the XFEL 30m
        Speakers: Julien Branlard (DESY), Dr Krzysztof Czuba Czuba (ISE)
        Slides
      • 11:25
        Main changes XFEL LLRF System & HGF Validation fond perspectives 25m
        Speaker: Dr Holger Schlarb (DESY)
        Slides
    • 12:00 → 13:30
      Lunch 1h 30m Restaurant in Lodex

      Restaurant in Lodex
    • 13:30 → 15:10
      Session 3 - LLRF uTCA Subsystems - Progress and Status Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 13:30
        MTCA.4 Platform Compatibility & Bugfixing 20m
        Speaker: Uros Mavric (DESY)
        Slides
      • 13:50
        Hardware & Firmware and Functionality of XxTIMER 20m
        Speaker: Holger Kay (DESY)
        Slides
      • 14:10
        KLM Status 20m
        Speaker: Mr Łukasz Butkowski (ISE)
      • 14:30
        uPS Design Status 20m
        Speaker: Dr Tomasz Jezynski (DESY)
        Slides
      • 14:50
        FMC25 Design and Status 20m
        Speaker: Mr Stefan Korolczuk (The Andrzej Soltan Institute for Nuclear Studies (IPJ))
        Slides
    • 15:10 → 15:30
      Coffee Break 20m Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
    • 15:30 → 17:00
      Working Groups Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 15:30
        Discussion: MCH, crates and power supply compatibility problems 5m
      • 15:35
        Discussion: Bug reporting applications and procedures 5m
      • 15:40
        Tutorial and discussion: how to set up MTCA system from scratch 5m
      • 15:45
        Discussion: Other problems presented during MTCA.4 Platform Compatibility & Bugfixing presentation. 5m
  • Tuesday 7 August
    • 08:30 → 10:00
      Session 4 - SIS Board HW/FW/SW Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 08:30
        Functional block diagram for SIS8300 15m
        Speaker: Mr Christian Schmidt (DESY)
        Slides
      • 08:45
        SIS8300L Design Status 25m
        Speaker: Dr Frank Ludwig (DESY)
        Slides
      • 09:10
        DWC8300FR 2.1 Design Status 25m
        Speaker: Mr Dominik Sikora (ISE, Warsaw University of Technology)
        Slides
      • 09:35
        SIS8300 Firmware Status 25m
        Speaker: Mr Wojciech Jalmuzna (DMCS)
        Slides
    • 10:00 → 10:30
      Coffee Break 30m Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
    • 10:30 → 12:00
      Session 5 - uTC Board HW/FW/SW Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 10:30
        Functional block diagram for uTC 15m
        Speaker: Mr Christian Schmidt (DESY)
        Slides
      • 10:45
        uTC (V6) specification & resource budget 25m
        Speaker: Mr Dariusz Makowski Makowski (Tech. Univ. of Lodz, DMCS)
        Slides
      • 11:10
        uVM Design Status 25m
        Speaker: Mr Igor Rutkowski (ISE, Warsaw University of Technology)
        Slides
      • 11:35
        uTC Firmware Status 25m
        Speaker: Mr Wojciech Jalmuzna (DMCS)
        Slides
    • 12:00 → 13:30
      Lunch 1h 30m Restaurant in Lodex

      Restaurant in Lodex
    • 13:30 → 15:00
      Working Group Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 13:30
        Tutorial and discussion: how to use DSP elements available in FPGA 5m
      • 13:35
        Discussion: documentation for LLRF systems 5m
      • 13:40
        Discussion: problems with timing modules 5m
      • 14:00
        Discussion: uTC resources and specification 5m
    • 15:00 → 15:30
      Coffee Break 30m Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
    • 15:30 → 17:00
      Session 6 - LLRF uTCA Subsystems - Progress and Status Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 15:30
        uDS86800 + RTM Design Status 20m
        Speaker: Mr Samer Bou Habib (ISE, Warsaw University of Technology)
        Slides
      • 15:50
        uRFB Design Status 20m
        Speaker: Dr Krzysztof Czuba (ISE, Warsaw University of Technology)
        Slides
      • 16:10
        uLOG Design Status 20m
        Speaker: Uros Mavric (DESY)
        Slides
      • 16:30
        ZONE 3 Classification 20m
        Speaker: Mr Dariusz Makowski Makowski (Tech. Univ. of Lodz, DMCS)
        Slides
    • 18:30 → 21:00
      Workshop Dinner Restaurant "Gęsi Puch" (Universe)

      Restaurant "Gęsi Puch"

      Universe
  • Wednesday 8 August
    • 08:00 → 09:40
      Session 7 - LLRF 19"Module Subsystems - Progress and Status Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 08:00
        TMCB 2.0 Revision Status 15m
        Speaker: Mr Jaroslaw Szewinski (Soltan Institute for Nuclear Studies)
        Slides
      • 08:15
        DCM Revision Status 15m
        Speaker: Mr Jan Piekarski (Warsaw University of Technology - Institute of Electronic Systems)
        Slides
      • 08:30
        LOGM Revision Status 15m
        Speaker: Mr Mateusz Zukocinski (Warsaw University of Technology)
        Slides
      • 08:45
        PZT Revision Status 15m
        Speaker: Mr Konrad Przygoda (TUL)
        Slides
      • 09:00
        PSM Status 10m
        Speaker: Mr Daniel Kuehn (DESY)
        Slides
      • 09:10
        MO Status 15m
        Speaker: Mr Lukasz Zembala (ISE, Warsaw University of Technology)
        Slides
      • 09:25
        REFM Revision Status 15m
        Speaker: Mr Dominik Sikora (ISE, Warsaw University of Technology)
        Slides
    • 09:40 → 09:55
      Coffee Break 15m Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
    • 09:55 → 11:30
      Session 8 - DOOCS Servers and Software for LLRF System Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 09:55
        Frontend server architecture and status 30m
        Speaker: Mr Adam Piotrowski (Technical University of Lodz, DMCS)
        Slides
      • 10:25
        New Naming Convention for DOOCS Servers 20m
        Speaker: Julien Branlard (DESY)
        Slides
      • 10:45
        Automation for DOOCS servers for AMTF 15m
        Speaker: Wojciech Cichalewski (TUL-DMCS)
        Slides
      • 11:00
        Middle layer server for loaded Q characterization 10m
        Speaker: Katarzyna Gnidzinska (DMCS/TUL)
        Slides
      • 11:10
        Recent FB & calibration results at FLASH LLRF System 20m
        Speaker: Mr Sven Pfeiffer (DESY)
    • 11:30 → 12:50
      Lunch 1h 20m Restaurant in Lodex

      Restaurant in Lodex
    • 12:50 → 13:55
      Working Group Main Auditorium A1/A2

      Main Auditorium A1/A2

      Department of Microelectronics and Computer Science

      ul. Wolczanska 221/223 building B18, 90-924 Łódź, POLAND
      • 12:50
        Discussion: problems with jDDD 5m
      • 12:55
        Discussion: universal server structure – how to develop server for different system 5m
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