8th MicroTCA Workshop for Industry and Research

3 Dec 2019, 08:00 → 5 Dec 2019, 18:00 Europe/Berlin

CFEL (DESY)

The 8th MicroTCA Workshop for Industry and Research will take place from 4 -5 December 2019 at DESY with pre-workshops on 3 December 2019.

The MicroTCA Technology Lab warmly invites you to participate in this workshop! The registration fee per person including coffee and lunch breaks, DESY tour, workshop dinner and workshop material is 190 Euro.   

Pre-Workshops and Tutorials require an additional fee (20Euro). All sessions will take place on Tuesday, December 3, 2019.                                                                 

 

If you have any questions please send an email to the MTCA Workshop support team

Tuesday, 3 December

09:00 → 12:00 Pre-Workshop

09:00 MicroTCA Plugfest

10:30 Signal Integrity

12:00 → 13:00 Lunch

13:00 → 18:15 Tutorials

13:00 DMA over PCIe with FPGA

Speaker: Mr Jan Marjanovic (DESY)

13:01 ATCA, AMC, microTCA: the form factors, available crate formats

Speaker: Mr Ralf Waldt (Schroff GmbH)

Slides ralf,waldt@nvent.com ralf,waldt@nvent.com

13:30 Communication links, clocks and triggers

Speaker: Kay Rehlich (DESY)

Slides MicroTCA_CommunicationClocksTriggers.pdf

14:05 Management basics and help to understand a MicroTCA system

Speaker: Mr Heiko Körte (N.A.T.)

15:00 Coffee Break

15:30 Development of a MicroTCA based Machine Protection System(MPS) at the Spallation Neutron Source (SNS)

Speaker: Mr Charles Roberts (Oak Ridge National Laboratory)

15:30 Introduction to ChimeraTK

Speaker: Martin Killenberg (DESY)

Slides killenberg_ChimeraTK_tutorial_dec2019.pdf

15:55 MPS @ XFEL & FLASH

MPS @ XFEL & FLASH

Speaker: Mr Juergen M. Jaeger (DESY)

16:20 MPS at ESS

MPS at ESS

Speaker: Stephane Gabourin (ESS)

16:45 MPS: hardware considerations

MPS: hardware considerations

Wednesday, 4 December

09:00 → 09:20 Welcome

Speaker: Dr Wim Leemans (DESY)

Slides 0_Welcome_V1R6TWA_final1.pptx

09:20 → 10:30 Session 1

09:20 Introduction

Speaker: Dr Holger Schlarb (DESY)

Slides 1_2019-12-04_8th-MTCAWS_HS_final.pdf 2019-12-04_8th-MTCAWS_HS_final.pptx

09:40 PICMG - 25 Years of Open Specifications for Embedded Computing

PICMG is a nonprofit consortium of companies and organizations that collaboratively develop open standards for high performance embedded computing applications, including MicroTCA. This presentation will review the 25 years of open specifications that have resulted from the work of hundreds of member companies. We will discuss both the current specifications, our development processes, and the value of PICMG membership. PICMG members benefit by participating in standards development, gaining early access to critical technology, and developing relationships with thought leaders and suppliers in the industry.

Speaker: Mrs Jessica Isquith (PICMG)

Slides PICMG_MicroTCA_Workshop_2019.pptx

10:00 Status of the MicroTCA-based Accelerator Control Systems at the European XFEL and FLASH

MicroTCA-based accelerator controls are nowadays widely used at the European XFEL and the FLASH facility. A brief review of the current status and some experiences with focus on the used MicroTCA technology will be shared. It was one of the key ingredients in the design of the accelerator controls for the European XFEL to use generalized solutions. Many of these now can be utilized for new projects at DESY and have been already implemented at accelerator research facilities and experiments at DESY. An overview of new MicroTCA-based accelerator controls projects and related projects at DESY will be presented.

Speaker: Dr Tim Wilksen (DESY)

Slides MTCAWS_2019_Tim_Wilksen.pdf

10:15 Status of ESS

Construction at ESS is proceeding. Commissioning of the first substantial section, the normal conducting Linac, is approaching. The talk gives an outline of the status of the control system preparations, concentrating on the MTCA-based systems. An overview of the developments and the control system architecture is given. Some results of newly developed applications are presented.

Speaker: Mr Timo Korhonen (ESS)

Slides MTCA4-at-ESS-MTCAWorkshop2019.pptx

10:30 → 11:00 Coffee Break

11:00 → 12:30 Session 2: Facility status reports

Convener: Mr Tobias Hoffmann (Helmholtzzentrum für Schwerionenforschung GSI GmbH)

11:00 Keynote: Fusion Research with MicroTCA applications

This presentation will provide an overview of the usage of MicroTCA systems at nuclear fusion facilities around the world. Many DAQ systems for fusion diagnostics at KSTAR (Daejeon, Korea) and Wendelstein 7-X (Greifswald, Germany) are currently based on the MicroTCA standard and their numbers are growing steadily. Also ITER, the next generation Tokamak, has committed to support MicroTCA as part of their DAQ portfolio. After a brief overview about nuclear fusion in general and typical diagnostic challenges, this talk will highlight a number of examples for existing MicroTCA-based systems and also provide an outlook regarding the future plans for MicroTCA at those facilities.

Speaker: Dr Axel Winter (MPI Plasmaphysik)

Slides 1_MTCA_in_Fusion_-_Winter.pptx

11:30 Summary of MTCA/ATCA workshop in China

Summary of the MTCA/ATCA workshop for research and industry at IHEP China in June 2018 is shown and future plans are also presented.

Speaker: Dr Xinpeng Ma (Institute of High Energy Physics, Chinese Academy of Sciences)

Slides 20191204_Summary_of_MTCAATCA_workshop_in_China.ppt

11:45 Survey on perceived strengths and weaknesses of MicroTCA.4

More and more scientific facilities have been adopting MicroTCA.4 as the standard for new electronics. Despite the advertised advantages in terms of system manageability, high availability, backplane performance and supply of high quality COTS modules by industry, the standard still lacks a greater acceptance in the accelerators community. This contribution will report on a survey carried out among the MicroTCA.4 adopters in the accelerator community to probe the perceived strengths and weaknesses of the standard and its ecosystem at present days.

Speaker: Mr Daniel Tavares (LNLS)

Slides A survey carried out among MicroTCA.4 adopters to probe the perceived strengths and weaknesses of the standard in the accelerators community.

12:00 MTCA is spreading in accelerator facilities in Japan

The application of MTCA for accelerators was pioneered by KEK. Although the development of the LLRF with MTCA at KEK was successful, it took time for the other accelerator facilities to employ MTCA-based systems. In these years, several applications of MTCA in Japan have been reported. The next-generation LLRF control system for the J-PARC RCS based on MTCA.4 was successfully deployed. A new MTCA-based LLRF system for an ion synchrotron is under development at WERC. There are more applications. The status of the application of MTCA in the Japanese accelerators and the future perspective are presented.

Speaker: Dr Fumihiko Tamura (J-PARC Center, Japan Atomic Energy Agency)

Slides MTCAWS_2019_tamura_191220.pdf

12:15 mini-CBM data acquisition system - status and outlook

The Compressed Baryonic Matter experiment (CBM) will be based at the new Facility for Antiproton and Ion Research (FAIR), which will deliver heavy-ion beams up to energies of 14 AGeV for N=Z beams. In nucleus-nucleus collisions at these beam energies strongly interacting matter with densities up to 10 times normal nuclear matter is expected to be produced. The key objective of CBM is to investigate the QCD phase diagram in the region of high baryon-densities, where a first order phase transition from hadronic to partonic matter as well as a chiral phase transition is expected to occur, representing a substantial discovery potential at FAIR energies. As a fixed-target experiment CBM is consequently designed to cope with very high interaction rates up to 10 MHz. This will allow to perform high precision measurements of extremely rare probes which have not been accessible by previous nucleus-nucleus experiments in this energy regime. To achieve the high rate capability CBM will be equipped with fast and radiation hard detectors employing free-streaming and self-triggered readout electronics. The newly built mini-CBM (mCBM) setup at GSI serves as technology demonstrator for the full CBM experiment. A prototype high performance Data Acquisition (DAQ) system for mCBM was built in 2018. In spring 2019 mCBM took first beam for a high rate system test of the detector systems, the free-streaming readout chain, the online time-slice building and online data monitoring in the First Level Event Selector (FLES). We will report on the current status of the mCBM DAQ system, which is based on microTCA hardware.

Speaker: Dr David Emschermann (GSI Helmholtzzentrum f. Schwerionenforschung)

Slides 20191204_169_mtca_desy_mcbm_daq_v01.pptx

12:30 → 13:30 DESY Tour 1

12:30 → 14:00 Lunch

14:00 → 15:45 Session 3: Products presentations

Convener: Dr Dariusz Makowski (Lodz University of Technology)

14:00 Keynote: Industrial high performance computing devices

Xilinx Roadmap and Tool setup -Alveo, high performance computing -Vitis, unified development tools -Versal, heterogeneous computing devices

Speaker: Mr Jens Stapelfeld (Xilinx)

Slides Xilinx_DESY_Talk_HH_Dec2019pdf.pdf Xilinx_DESY_Talk_HH_Dec2019pdf.pptx

14:30 MTCA goes industry

The most convincing feature of an MTCA system are its multiple uses. With the same basic system and different AMCs, almost all requirements in the industry can be met. Representing all industrial applications, this presentation only shows applications in image processing and communication.

Speaker: Mr Friedrich Fix (Sales)

Slides 2_pBC_2019-12-04_MTCAWS_MTCA_goes_Industry.pptx

14:45 The diversity of MTCA

MTCA offers a variety of uses for various applications such as accelerator control systems, medical beam diagnostics, video conferencing, image processing, and more. The wide selection and availability of AMC processors and peripheral cards allows us to build MTCA systems for every customer application. This presentation shows suitable solutions for applications based on examples of communication technology and image processing. That's why we call MTCA: Universal Data Acquisition Computing System (UDAC).

Speaker: Mr Tim Dally (Sales)

Slides 3_pBC_The_diversity_of_MTCA.pptx

15:00 MTCA.4 Applications for Accelerators: Machine Protection System and Photon Beam Stabilization Exploiting DAMC-FMC25

This contribution aims to show how MTCA.4 is used for the development of accelerator systems for diagnostics and photon beam stabilization exploiting the DAMC-FMC25 AMC carrier board features. We present the system architecture, the final application and some preliminary results regarding a Machine Protection System (MPS) and an Electron Beam Stabilization System (PBSS) in research facilities. The MPS is composed by a third-party control board that communicates with multiple AMC-PICO-8 8-channel picoammeters developed by CAEN ELS. The AMC-PICO-8 stores acquired data buffer up to 1 Msps, generates a MPS signal upon specific over-threshold conditions and stops the acquisition after a post-mortem signal. The PBSS elaborates the information received from a position detector via the FMC-PICO-1M4 picoammeter front-end, performs the feedback controller computations (IIR filter) and sends the correction signals directly to the FAST-PS power supplies equipped with fast low-latency SFP interfaces. The communications with backplane (PCIe) and FMC modules (SPI) and all the high demanding computations are handled by the FPGA available on the DAMC-FMC25.

Speaker: Dr Paolo Scarbolo (CAENels)

Slides 4_20191201_MTCA_Workshop_CAENELS_Scarbolo_v3.pptx

15:15 Available MTCA.4 Crates and their Backplane Topologies

This presentation gives an overview of the nVent SCHROFF Standard MTCA.4 Crate solutions and the various backplane topologies. Showing the different cooling concepts, slot orientations and arrangements and system features as well as additional backplane connectivities. Furthermore a short outlook of the upcoming Crate solutions will be presented.

Speaker: Mr Christian Ganninger (nVent)

Slides nVent_SCHROFF_MTCA.4_Crates.pptx

15:30 DAMC-FMC2ZUP a MPSoC based FMC+ carrier card

The ecosystem of FMC/FMC+ carriers in MicroTCA (Advanced Mezzanine Card form factor) is very diverse. The requirements for such a board are very demanding, sometimes even opposing to each other, and the definition of a specification that will satisfy most of the use cases without crossing the boundary of the 80W available for an AMC card is a challenging task. Presented here is the DAMC-FMC2ZUP, a modern and high-performance FMC+ carrier in AMC form factor, that hosts a Xilinx Zynq UltraScale+ MPSoC. The FPGA has a total of 52 transceivers (32 GTH, 16 GTY, 4 GTR) providing support to the diverse communication interfaces towards the FMC slots, backplane and RTM. The four cores ARM-A53 processor with Mali graphics, and the availability of DisplayPort and USB interfaces over the USB type-C connector allow to use this board as a replacement to an additional CPU card for not so high demanding applications. The availability of an independent dual core ARM-R5 that is certified for safety critical applications allows the user to implement either or both real-time and safety related applications. The design supports different methods of synchronization to an external timing system and already includes all the necessary electronics to implement a White Rabbit endpoint when paired with the external SFP breakout board. DAMC-FMC2ZUP is a versatile platform ideal to perform control tasks around a particle accelerator. Combined with the modularity of the MicroTCA platform it can be a building block for a larger system. The discussion will be concluded with an overview of possible approaches to overcome the power limitations in the future.

Speaker: Mr Simone Farina (DESY)

Slides MTCA_Workshop_2019.12.04_DAMC-FMC2ZUP_a_MPSoC_based_FMC+_carrier_3Dec2019_clean.pptx

15:45 → 16:15 Coffee Break

15:45 → 16:15 Poster session

15:45 The new revision of the MicroTCA.4-based 8 Channel, Direct Sampling, Single Channel Up-Converter Board

Extensive measurements of the DRTM-DS8VM1 gave insight into which sections on the module can be further improved. Among all the various features that were tested we present the latest results of AC and DC channels noise spectral densities. Preliminary results of the long-term drift compensation are also presented. Finally, the major changes being implemented on the board are presented.

Speaker: Uros Mavric (DESY)

15:46 Precision X-band RF control system

The new PolariX TDS and its tomographic capabilities will be used in FLASH2, FLASHForward and SINBAD and shall provide a new level of beam diagnostics. It is developed in cooperation between DESY, PSI and CERN and requires X-band RF front-ends for the measurement of the 12 GHz electric fields. The cavity, waveguide and klystron signals will be down-converted from 12 GHz to 3 GHz and further processed in a standard 3 GHz S-band LLRF system based on MicroTCA.4. We will present the methods used to convert the signals as well as providing an overview of the MicroTCA.4 functions used in this setup. Measurements have shown a short-term jitter of less than 1.5 fs rms added by the conversion system.

Speaker: Mr Matthias Reukauff (DESY)

15:47 DAQ system for energy dispersive gamma and X-ray detectors

We present a new data acquisition system for energy dispersive X-ray and gamma detectors based on the MicroTCA.4 standard, which has been developed for photon science applications at DESY's brilliant X-ray source PETRA III. At the center of this development is a new real-time pulse shape analysis algorithm and trigger system. Due to the noise reducing properties of the algorithm, the data are very clean and a very low threshold value can be achieved. With a previously developed firmware framework[1] we have implemented the new algorithm in the Field Programmable Gate Array (FPGA) of the commercialized SIS8300L card[2]. This ten-channel, fast ADC card was used in conjunction with an amplifier rear transfer module (DRTM-AMP10) developed by the authors and optimized for energy dispersive detectors. In combination with our control software, this data acquisition system offers a high energy resolution of 130 eV FWHM at 5.4 KeV with a peaking time of 560 nanoseconds (measured with an Amptek detector) and supports counting rates of more than 10^6 counts per second and enables continuous data acquisition without conversion time. It provides highly accurate time information for a wide range of detector types up to one clock cycle (8 ns), independent of the deposited energy, thanks to the constant fraction discriminator similar features of the algorithm. In supported file formats such as HDF5 and ROOT, various data is provided, ROI, histogram, extended event information up to the total pulse shape for each event. Thanks to the MicroTCA.4 standard, advanced clocking and triggering as well as high data throughput via PCIe and scalability are possible. The financial support of the project by the DESY Strategy Fund is recognized. References 1] L. Butkowski et al., "FPGA Firmware Framework for MTCA.4 AMC Modules" Proc. 15th Int. Conf. on Accelerator and Large Experimental Physics Control Systems (ICALEPCS'15), Melbourne, Australia, Oct. 2015, paper WEPGF074, p. 876--880 2] Struck Innovative Systems. 2018 SIS8300-L MTCA.4 Digitizer. [ONLINE] Available at: http://www.struck.de/sis8300-l.html. [accessed November 2, 2018].

Speaker: Dr Jan Timm (DESY)

15:48 Investigation of MTCA power supply problem after power glitch.

During the operation of many MTCA based systems, we noticed problems after power glitches. The presentation treats on investigations of the problem. Thanks to the collaboration with the power supply manufacturer the observed problem with MTCA power supply was solved by a firmware upgrade.

Speaker: Dr Mariusz Grecki (DESY)

15:49 Future perspectives for LLRF Systems in MicroTCA

In the talk we present the R&D at DESY to enhance the capabilities of future LLRF systems. This includes improvement and performance evaluation of current boards, extensions toward attosecond field receivers and supplementary modules that ease LLRF operations.

Speaker: Dr Frank Ludwig (DESY)

15:50 Status and preliminary Test of LLRF System for the MESA Project

The Mainz Energy-recovering Superconducting Accelerator (MESA) is currently under construction at the Institut für Kernphysik (KPH) at Johannes Gutenberg-Universität Mainz. MESA is a multi-turn Energy Recovery Linac (ERL) and aims to serve as user facility for particle physics experiments. The RF-accelerating systems of MESA consist of two cryomodules, each with two 9-cell TESLA superconducting (SC) cavities, and eight normal conducting cavities. They operate in continuous wave (CW) mode. The MicroTCA.4 based digital low-level radio frequency (LLRF) system developed at DESY, Hamburg is adapted for the MESA cavities to guarantee a cavity accelerating field amplitude and phase RMS stabilities of 0.01% and 0.01$^{\circ}$. In this presentation, a LLRF system test with a stand alone normal conducting MESA single cell buncher cavity is shown. The amplitude and phase stabilities of the test are 0.05% and 0.05$^{\circ}$ respectively, which are limited by the stability of the master oscillator of the test bench. Furthermore, the overview of the LLRF system integration into the MESA cryomodules test bench at Helmholtz-Institut Mainz (HIM) test bunker is presented, as well as the preliminary LLRF test results at a temperature of 2 K. The RMS stability requirements are not yet reached due to the lack of the frequency detuning control and the controller parameter optimization. Both are still under development.

Speaker: Dr Jiaoni Bai (Institut für Kernphysik , Johannes Gutenberg-Universität Mainz)

15:51 Status of MicroTCA Implementations at the Spallation Neutron Source

The Trigger Control, Injection Kicker Waveform Monitor and Ring Low Level RF systems at the Spallation Neutron Source are currently operating with MicroTCA based solutions. MicroTCA based Machine Protection System is installed on segments of the machine and under testing. A 16 channel 2 GS/s coherent sampling Extraction Kicker Waveform Monitor with segmented memory acquisition mode is in early development using MicroTCA. Also, under development using MicroTCA is a safety pedigreed Beam Power Limiting System. This poster will cover those and other MicroTCA efforts at the SNS.

Speakers: Mr Charles Roberts (Oak Ridge National Laboratory), Mr Eric Breeding (Oak RIdge National Laboratory)

15:52 MicroTCA Technology Lab (A Helmholtz Innovation Lab): A Status Update on Current Activities

Helmholtz Innovation Labs (HILs) have been established throughout Germany since 2016 to create enabling spaces for the interaction of large public research centers with industry. Possible areas of cooperation include joint product development or improvement, demonstration and test of novel industry solutions and business models, marketing and training as well as supporting activities for ermerging user communities. Within the HIL-framework, DESY has established the MicroTCA Technology Lab with the following core activities: • High-end test and measurement services, • Customer-specific developments in MicroTCA (hardware, firmware, software), • Turn-key System configuration and integration. Officially opened in April 2018, our lab has delivered projects in industry and research in these areas while maintaining links to a wide spectrum of industry partners, supporting the further enhancement of the MicroTCA standard by contributing to development initiatives within the framework provided by PICMG.

Speaker: Dr Thomas Walter (DESY)

15:53 Drift Compensation Measurements of RF Field Detectors operating in CW Mode and based on MicroTCA.4 Standard

Drift Compensation Measurements of RF Field Detectors operating in CW Mode and based on MicroTCA.4 Standard

Speaker: Uros Mavric (DESY)

15:54 DESY MMC System on Module and its application on a low-cost FMC carrier

A complete MMC System-on-Module was developed. It is s a small stamp-sized (25x29x2.3 mm) component which can be mounted on top or bottom side of any AMC card. The module handles the complete communication to the MCH. For basic operation, the user boards needs virtually no additional components to allow management and power delivery from the system. The SoM is pre-programmed and contains an ARM Cortex-M4 microcontroller and a CPLD. It provides advanced features such as JTAG arbitration (allows acces from JTAG switch module), in-system programming (via IPMI/HPM) of the module and up to two user FPGAs, PMBUS power management, RTM handling and RTM power delivery. The Low-Cost Zynq-7000 based FMC Carrier DFMC-FMC1Z7O is based on this MMC module. It contains a XC7Z030 or XC7Z045 FPGA and 1 GB on-board DDR3 memory. The board is designed for controlling RTMs, offers 48 digtal IOs (selectable 3.3V and 5V I/O) on the front panel and provides an FMC slot for expansion with up to four high-speed transceivers (MGTs) with up to 10Gbps data rate.

Speaker: Mr Michael Fenner (DESY)

16:15 → 18:00 Session 4: Future of MicroTCA

Convener: Mr Christian Ganninger

16:15 MicroTCA Next Generation: Plans for the Future

The next generation of CPUs will support PCIe gen 5. And to allow faster CPUs more power is required for AMCs. To address these challenges a new PICMG working group is in preparation. Goals and options to keep MicroTCA as a leading standard will be presented.

Speaker: Kay Rehlich (DESY)

Slides MicroTCA_NextGeneration.pptx

16:30 Teledyne e2v, multi GSPS ADC/DAC roadmap

Teledyne e2v product Roadmap and Tool setup -ADC, up to 6.4 Gsps -DAC, up to 8 Gsps -ESIstream, resource optimized ADC/DAC protocol

Speaker: Mr Jens Michaelsen (Avnet Silica)

Slides Te2v_microTCA_Desy_2019.pdf

16:45 From 40G to 100G - a new MCH concept

Increasing demands for modularity and bandwidth create a constant challenge to meet the requirements of application from the “low end” (i.e. Industrial IoT) to the “high end” (i.e. data processing with high-end FPGAs). Therefore, in the long term a new concept for the MicroTCA Carrier Hub (MCH) is needed which allows a flexible mix-and-match of MCH sub-modules and provides state-of-the art switching technology for slim and fat-pipe fabrics at the same time. The presentation will show how this transition from existing MCHs to future solutions can be smoothly effected while maintaining a maximum on backward compatibility.

Speaker: Mr Heiko Körte (N.A.T.)

Slides S4_T3_from_40G_to_100G.pdf

17:00 Trends that are Influencing Intel Processor based AdvancedMCs

Historically, an Intel processor based AdvancedMC module was used as the central control station in a MicroTCA system to display status information, provide local storage and to act as a gateway between the other boards in the system and the outside world via a network connection. That’s an important function and has become elevated as this board typically can act as the root of trust in a system. To do that we include a variety of security technologies and features that should be of interest given the sensitive nature that the products are controlling. In addition, more users are using compute intensive Intel processor based AdvancedMCs for local data processing. Whilst Intel CPU only solutions offer significantly less processing capability compared to GPU and FPGA based solutions, they are much easier to program and by using Intel’s OneAPI, it is possible to add co-processors like FPGA without code changes. In this type of heterogeneous scenario, OneAPI will optimise the code to use the available processing resources in a similar way to that of OpenVINO which is specific to Artificial Intelligence and Inference at the Edge applications.

Speaker: Mr Paul Prictoe (Concurrent Technologies Plc)

Slides MicroTCA_Workshop_2019_CCT.pptx

17:15 A new Zone 3 Class for RF Signals up to 3 GHz in MicroTCA.4

In MicroTCA.4 the connection between AMC and RTM is realized with a differential pair connector. Transporting high frequency analog signals (> 300 MHz) over the differential pair connector leads to intense crosstalk between the differential channels. A new type of Zone 3 connection is needed, capable of transporting signals up to 3 GHz. The new analog Zone3 class RF1.0 based on single-ended coaxial connectors will be presented. First measurement data from several evaluation boards showing the single-ended performance and isolation of the new coaxial connectors will also be presented. The class RF1.0 can be used for direct sampling application feeding RF signals from the RTM to the AMC side or for RF sampling DAC applications in the opposite direction.

Speaker: Mr Johannes Zink (DESY)

Slides 5_AnewZone3ClassforRFSignalsupto3GHzinMicroTCA4.pptx

17:30 Overview of MicroTCA Techology Lab activities

In its second year of operation has MicroTCA Technology Lab continued to foster the MicroTCA community and deliver customer-oriented solutions. We observe that the MicroTCA market is growing and more and more institutes are adopting or considering adopting MicroTCA as a platform for future installations. We present here the projects where MicroTCA Technology Lab was involved last year. To name a few: we have successfully delivered turn-key LLRF systems, certified our GigE Vision FPGA implementation and enhanced it with 10 Gigabit Ethernet version, developed a new Zone 3 class for high-frequency RF signals, productized our MMC implementation in DMMC-STAMP and developed a Zynq UltraScale+ MPSoC-based FMC+ carrier. We have also rethought and redesigned MTCA training courses, to give them more emphasis on the needs of the experimental physics. Together with our colleagues from IHEP we have organized the first MicroTCA Workshop in China, and we are determined to continue this tradition also in the years to come. We have also participated at several conferences and organized several single-day events. We conclude this overview with a brief summary of the upcoming projects.

Speaker: Mr Jan Marjanovic (DESY)

Slides mtcaws2019_techlab_overview.pdf

17:45 Electromagnetic Compatibility (EMC) in Modern Eletronic Standards e.g. MicroTCA.4

Speaker: Dr Frank Ludwig (DESY)

Slides 2019_MTCA4_EMC_in_Modern_Standards_04_12_19_FLudwig_Short2.pdf

19:00 → 22:00 Dinner

Thursday, 5 December

09:00 → 10:30 Session 5: Subsystems

Convener: Mr Heiko Körte (N.A.T.)

09:00 MTCA based BPM system design

A digital beam position measurement system based on MTCA.4 is designed. The system includes a RF front-end circuit and a digital signal processing module. The RF front-end circuit adjusts the signals from the beam position detectors to meet the requirements of the analog to digital converter. The digital signal processing algorithm is implemented in the FPGA. Multi-rate signal decimation, CORDIC algorithm, difference-over-sum algorithm are implemented in the FPGA.Data on demand at Turn-by-Turn(revolution) frequency(TBT data), fast acquisition data(FA data) and slow acquisition data(SA data) are obtained after the digital signal processing in the FPGA.The hardware system is based on MTCA.4 with high integration and reliable performance and the RF front-end gain can be adjusted through the serial port flexibly.

Speaker: Ms Yu Liang (National Synchrotron Radiation Laboratory,USTC)

Slides MTCA_based_BPM_system_design_-2.pptx

09:15 Overview of DMCS Projects and MicroTCA.4 Developments

The Lodz University of Technology, Department of Microelectronics and Computer Science is involved in the development of MicroTCA.4 and MicroTCA.4.1 standards from 2007 onwards. Since that time, we developed various MicroTCA.4 components including Intelligent Platform Management, Advanced Mezzanine Cards (AMCs), Rear Transition Modules (RTMs) for data acquisition and processing systems used in numerous accelerators and fusion projects. The presentation will discuss a selected projects ongoing at our department based on MTCA.4 technology.

Speaker: Dr Dariusz Makowski (Lodz University of Technology)

Slides 2_Dariusz_Makowski_MTCA.4_Workshop.pdf

09:30 MTCA.4 BASED BUTTON AND STRIP-LINE BPM ELECTRONICS AT DESY

We present a new BPM electronic for button and strip-line monitors based on MTCA.4. The system is used for Beam position measurement and as an part of an array also for energie measurement. The electronic is installed at nearly 100 BPMs and EBPMs. We summarize the recent analog and digital hardware development and operational experience at FLASH, XFEL and Pitz.

Speaker: Mr Hans-Thomas Duhme (DESY)

Slides uTCA-WS19-duhme.pdf

09:45 A MicroTCA Based Design for HEPS Global Timing System

The High Energy Photon Source (HEPS) is a fourth generation synchrotron radiation light source with top electron energy of 6 GeV stored in a 1360-m circumference storage ring and a low emittance of less than 0.06nm·rad which is scheduled to complete its construction by the end of 2025. Because of high precision requirements of storage ring swap-out injection and extraction, the bottom width of the kickers’ pulse need to be shorter than the separation between two bunches which is 12ns. Consequently, a high precision global timing system with an accuracy about 10ps has to be designed and implemented. This talk will outline the MicroTCA based global timing system design and report the progress of the high precision AMC timing receiver in the event-based timing system.

Speaker: Ms Fang Liu (Institute of High Energy Physics)

Slides A_MicroTCA_Based_Design_for_HEPS_Global_Timing_System.pptx

10:00 Insight on failures of MTCA systems installed in FLASH and EuXFEL tunnels

FLASH has been operated with MTCA.4-based LLRF systems since 2013 and the European XFEL since 2017. We are now starting to see some failures which could be related to the fact that these systems are placed in a radiation prone environment. This contribution aims at presenting a first insight on the impact of radiation on the MTCA.4 system. In particular, the different shielding types and the different ways of measuring radiation is shown. Correlation between hardware or firmware failures with the measured radiation is presented. Some mitigation strategies are also discussed. Other failures linked to power glitches or loss of pcie communication will also be presented.

Speakers: Mr Christian Schmidt (DESY), Dr Julien Branlard (DESY)

Slides 2019_12_05_-_Radiation_MTCA_v6.pptx

10:15 Magnetic and Radiation Field Compatibility of MTCA and PXIe based Instrumentation

Electronics exposed to magnetic or radiation fields are susceptible to components failures or performance degradation. In 2012 studies of MTCA and PXIe systems have been performed at DESY for magnetic fields and for radiation fields at ENEA, JSI and Atomki. In this presentation the results of these tests will be summarized.

Speaker: Dr Stefan Simrock (ITER)

Slides 6_Magnetic_and_Radiation_Field_Compatibility_MTCA_Simrock.pptx

10:30 → 11:00 Coffee Break

10:30 → 11:00 Poster session

11:00 → 12:30 Session 6: FPGA

Convener: Mr Thomas Holzapfel (Industry Partner)

11:00 Keynote: RFSoC, high performance data processing devices with multi GSPS ADC/DAC

Xilinx RFSoC Roadmap and feature set -Gen 1,2,3, … multi GSPS ADC/DAC SoCs -Scalebility and Migration path -from 1 to 100 G-Bit Ethernet -ERNIC/RDMA sever offloading

Speakers: Mr Jens Michaelsen (Avnet Silica), Mr Michael Oelmann (Xilinx)

Slides 191118_Zynq_UltraScale+_RFSoC_uTCA_v2.pdf 191118_Zynq_UltraScale+_RFSoC_uTCA_v2.pptx

11:30 IRIO-OpenCL: Simplified development and integration of DAQ and processing systems using OpenCL for IntelFPGA devices

Many frameworks exist to ease the integration of FPGA based systems into the Instrumentation & Control systems that are required on Big Science facilities. We present a new approach, using the heterogeneous programming language OpenCL to design and develop acquisition and processing applications. This approach reduces the usage of HDL languages significantly to describe the hardware on the FPGA, shortens the development cycle for compliant COTS solutions, and is well suited for the heterogeneous environment that is often found on Big Science experiments. The work presented here is a set of methods and tools that allow developing applications for FPGA-based instruments in a standardised way. The framework comprises elements such as: an OpenCL compliant Board Support Package with a PCIe interface; an OpenCL IO channel to communicate with high-speed AD/DA converters using the JESD204B standard; a set of OpenCL Kernels to support common DAQ functionality, capable of acquiring and processing at high sampling rates; and a standardized software interface, including the ITER Nominal device Support (NDSv3) software layer that integrates the whole solution with EPICS. On the hardware side, the system has been implemented in an MTCA chassis with a carrier hub, which provides an optical PCIe (gen3) interface, connected to the host computer. The Advanced Mezzanine Card (AMC) module is the N.A.T Advanced Mezzanine Card NAMC-Arria10-FMC . This board mounts an IntelFPGA ARRIA10-SoC and includes an FMC (FPGA Mezzanine Card) connector where the Analog Devices AD-DAQ2FMC-EBZ module providing two 1GS/s ADC channels together with two 1GS/s DAC channels. An example use case for data acquisition and processing system was implemented to estimate the e the average neutron flux emitted by the plasma in a fusion experiment. The DAQ system digitises the pulses produced by the neutrons in the fission chamber and, applies hardware signal processing algorithms to estimate the neutron flux: Pulse Counting, Campbelling, and Current counting. All the high-performance tasks of acquiring and processing involved in the algorithms are carried out by OpenCL Kernels, which, as a result of the compilation process, are implemented in hardware that is deployed in the FPGA.

Speaker: Mr Miguel Astrain (Universidad Politecnica de Madrid)

Slides IRIO-OpenCL

11:45 Certification and improvements of MicroTCA Technology Lab’s GigE Vision Stack

The DIPC-7050 GigE Vision Stack is a system solution for running GigE Vision cameras in a FPGA/SoC- based environment. It is usable in wide array of industrial and scientific applications. By integrating the component in their system users are able to create and run their own high performance image processing solutions without taking care of any camera interfacing; especially without taking care of the GigE Vision standard. This talk outlines the latest developments and improvements of the DIPC-7050 GigE Vision Stack. We present the results of the products standard certification at AIA plug-fest, where our implementation had to interface with cameras from several vendors. Our implementation is now officially certified as a GigE Vision compliant product. For covering the increasing demand of higher data throughput, the GigE Vision standard offers a 10Gigabit Ethernet variant. In the last couple of month we upgraded our solution for operating with devices via 10 Gigabit Ethernet. We present the improved version and discuss the performance.

Speaker: Sven Stubbe (DESY)

Slides gige_vision_update_stubbe_20191205.pdf

12:00 Modernization of MicroTCA.4 FPGA Firmware Framework

MSK group in DESY has been working on a common framework to develop FPGA firmware for MicroTCA standard for over 15 years. This highly modular, abstracted framework has been used to deploy many accelerator facilities inside and outside of DESY. With increasing complexity, maintenance and continuous integration becomes critical in order to ensure minimal downtime for FPGA firmware related failures. This talk gives overview on the framework as well as future upgrades on interfaces, revision control and continuous integration.

Speaker: Mr Cagil Guemues (DESY)

Slides mtca_ws_2019_presentation.pdf

12:15 FPGA Configuration and Monitoring via Ethernet in MicroTCA

In the European XFEL (EuXFEL), the MicroTCA.4 platform hosts Advance Mezzanine Cards (AMCs) with FPGAs for data acquisition, processing and timing distribution. Communication with these devices, to configure, monitor and receive raw and process data, is done via PCI Express (PCIe) using a CPU AMC. In some setups, FPGAs are not used for data acquisition but transmit information to devices outside of the MicroTCA crate (for example detectors). The FPGA device is configured in the beginning of an experiment and periodically monitored afterwards. In these cases, the CPU's sole function is to provide PCIe communication, increasing the cost and configuration complexity per crate. Since the MCH can also communicate via Gigabit Ethernet with the AMCs of the crate, we can bypass the need for a CPU in the crate by developing an Ethernet protocol to communicate with the FPGAs. In addition, for setups where the data volume is not significant, this communication method can also be used to send raw and process data directly from the MCH to our DAQ system. In this presentation, we will demonstrate how such communication is being develop in the EuXFEL.

Speaker: Mr Nuno Gonçalves (Universidade de Lisboa, XFEL GmbH)

Slides MicroTCA_workshop_Eth2II_NG.pdf

12:30 → 13:30 DESY Tour 2

12:30 → 14:00 Lunch

13:00 → 14:00 DESY Tour 3

14:00 → 16:00 Session 7: Facility Status Reports

Convener: Dr Axel Winter (Max Planck Institut für Plasmaphysik)

14:00 Overview and experience related to MicroTCA applications at the European XFEL Experiments

Since start of user operation two years ago, the European X-Ray Free Electron Laser facility (European XFEL) is relying on the MicroTCA platform for timing distribution, data processing from large 2D detectors, fast digitization and processing of pulse signals as well as low latency communication protocol for VETO and Machine Protection System. To cope with the experiments that use the generated ultra short coherent X-Ray flashes, spaced by 220 ns and with a duration of less than 100 femtoseconds, almost 40 individual MicroTCA systems are used at the photon beam lines and experiments, all fully integrated in our control and DAQ systems and monitoring solution to immediately identify problems if they occur. Our experience with the platform grows in parallel with user requests for more particular and challenging case studies and tailor made hardware algorithms. This requires integration of new hardware and, at the same time, taking advantage of MicroTCA features that where not in use before. In this presentation, we will provide an overview of the MicroTCA platform in our environment, results and experience from last years experiments, as well as an outlook to future developments.

Speaker: Mr Bruno Fernandes (European XFEL)

Slides mtcaWorkshop2019_BF.pdf

14:15 Firmware and software synchronization for MicroTCA roll-out in the LLRF at CERN

During the long shutdown from 2019 to 2020, CERN's Super Proton Synchrotron (SPS) is undergoing a comprehensive upgrade of its Low Level RF system, using MicroTCA as a hardware platform. The new system, currently under development, attempts to maximise firmware reuse by implementing its functionality as independent IP cores, each of which must be supported by corresponding software components which interface it to the accelerator control system. Any changes in the HDL need to be followed consistently by changes in the software layers. This talk will present an overview of the software stack and tools which have been developed to synchronize the firmware and software during the development process.

Speaker: Mr Maciej Suminski (CERN)

Slides fw_sw_sync_mtca.pdf

14:30 ALBA DLLRF using commercial uTCA platform

The Digital LLRF of ALBA has been implemented using commercial cPCI boards with Virtex¬4 FPGA, fast ADCs and fast DACs. The firmware of the FPGA is based on IQ demodulation technique and the main feed¬back loops adjust the phase and amplitude of the cavity voltage and also the resonance frequency of the cavity. But the evolution of the market is moving towards uTCA technology and due to the interest of this technology by several labs, we have developed at ALBA a DLLRF using a HW platform based on uTCA commercial boards and Virtex¬6 FPGA. Also, a new approach based on commercial AMC boards modified to be used as standalone products has been studied. Stand-alone boards can be a good solution for low budget projects where no interconnections between different modules are needed. This presentation will cover these development and the main differences between them.

Speaker: Angela Salom (ALBA)

Slides 20191205_-_ALBA_DLLRF_using_commercial_uTCA_platform.ppt

14:45 Overview of the MYRRHA project and its LLRF MTCA developments

This talk will discuss the status of the MYRRHA project with a focus on the current and planned LLRF developments for the first phase of the project

Speaker: Mr Wouter De Cock (SCK-CEN)

Slides MYRRHA_MTCA_-_Hamburg2019.pdf

15:00 Development of MTCA.4-Based LLRF System at SSRF

Since we got the first MTCA.4 platform in 2014, MTCA.4-based Low Level RF system has been widely used in many linear accelerators at SSRF. This talk gives an introduction of all accelerator projects, the development of the software and the firmware, and also the performance of the LLRF system.

Speaker: Dr Junqiang Zhang (Shanghai Advanced Research Institute,CAS)

Slides Development_of_MTCA.4-Based_LLRF_System_at_SSRF.pdf

15:15 Influences for the cooling performance of a MTCA.4 Crate

A MicroTCA Crate shall be capable to cool 80W per slot under standard conditions. This presentation shows under which circumstances the cooling performance is tested by the crate vendor. Based on real experience it will show how different slot air impedances, air short cuts or air blocks affects the cooling performance of the crate.

Speaker: Ralf Waldt (nVent Schroff GmbH)

Slides nVent_Influence_Cooling_Performance.pptx

15:30 Device error handling in ChimeraTK

ChimeraTK is a tool kit to write application servers for control systems. When integrating devices into a control system, the device servers usually contain a large fraction of error handling code. Many of these errors are runtime errors which occur when communicating with the hardware. Not only malfunctioning of the hardware can cause these errors, but also a board which is turned off via the hot-plug mechanism in a MicroTCA crate. We report how ChimeraTK introduces a standardised way to raise and report errors, and to do the re-initialisation when recovering from an error. All this is handled in the framework, which significantly simplifies the business logic because it is not mixed with error handling code any more.

Speaker: Martin Killenberg (DESY)

Slides killenberg_ChimeraTK_device_error_handling2019.pdf

15:45 Redundant CPU on MicroTCA System with PCI Express Non Transparent Bridge

One of the main characteristics of any control system is reliability and uninterrupted operation. Reaching that lofty target, however, requires more than having reliable hardware, hot-swap repair capabilities and robust software design. High availability need help from many redundant components, including redundant CPUs. The PCI Express standard is currently the most widely used architecture. The MTCA as well as the majority of architectures today use the PCI Express as a central bus of data transmissions. To protect against a failing CPU taking the entire system down, a backup CPU can be in place, ready to take over. One method is to have a secondary CPU behind an Non Transparent Bridge and use Non Transparent Bridge failover sequence. Our experience of the adjustment, starting and testing as well as use of the Redundant CPU on the MTCA system will be presented.

Speaker: Mr Ludwig Petrosyan (DESY)

Slides RedundantCPU_NTB_Workshop2019.pdf RedundantCPU_NTB_Workshop2019.pptx

16:00 → 16:10 Closeout

Speaker: Dr Holger Schlarb (DESY)

Slides 2019-12-04_8th-MTCAWS_close_out_HK.pptx

16:10 → 16:40 Coffee