The 10th MicroTCA Workshop for Industry and Research will take place from 7-9 December 2021 at DESY.
The main topics of the workshop are:
DESY warmly invites you to participate in this workshop! The registration fee is 50 Euro.
If you have any questions please send an email to the MTCA Workshop support team
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Engineering a completely new MicroTCA system can be a daunting task for people with little experience in the MicroTCA field. Since the standard is quite flexible, the 'correct' choice can be sometimes ambiguous. The purpose of this tutorial is to give tips and tricks to people who are relatively new to the MicroTCA systems. It covers many sub-categories of system design including; choosing the right hardware, FPGA programming, and software development in MicroTCA systems.
MTCA-based systems are nowadays widely used at many of DESY's accelerator facilities. A brief review of the current accelerator controls status and some experiences with focus on the used MTCA technology will be shared. After the successful implementation of MTCA at the European XFEL and FLASH facilities meanwhile this hardware standard and platform made its inroads into the various new projects and accelerator research and development programs at DESY. An overview of these and related projects at DESY will be presented.
The SPS LLRF system was completely upgraded during CERN Long Shutdown 2 (Jan 2019-March 2020). The new Beam Control implementing the beam-based Loops (radial and phase) and the frequency program (B to revolution frequency) is implemented on the MicroTCA platform. The AFCZ (AMC FMC Carrier with Zynq) and QSFP-RTM are used to interface with ADCs, two White Rabbit networks and 10 Gbps serial links. This modular system combined with a powerful Zynq SoC allows for the real-time control of our 8 RF cavity controllers and RF-synchronous equipment. The beam pick-up signals are direct sampled using FMCs with 125 Msps ADCs and later 5 Gbps enabling bunch-by-bunch processing and control. This presentation describes the architecture of the SPS Beam Control and the performance obtained with the MicroTCA platform after several month of beam commissioning with proton Fixed-Target, proton LHC and Lead ions beams (April 2021 – present).
The University of Hamburg, in collaboration with DESY, is developing an electrical ground-support equipment phasemeter, or phasemeter simulator, based on the MicroTCA.4 standard, for the space-based gravitational wave detector LISA, funded by the German Aerospace Agency (DLR). The main task of the phasemeter is to extract the phase of various laser interferometer beat note signals with microcycle precision at frequencies between 0.1mHz and 1Hz. Additional functions include the readout and generation of ranging and data communication sidebands, frequency control of the lasers and signal acquisition.
The development is conducted in parallel to, and in collaboration with, the development of the flight hardware phasemeter and the simulator will be made available to the partners within the LISA consortium for the assembly, integration, verification and testing (AIVT) phase of the mission and for the technology development of payload items. We present the system design, results of a custom phase fidelity testing setup and the status of our hardware development.
The Spallation Neutron Source is currently upgrading its accelerator power level from 1.4 MW to 2.8MW via the Proton Power Upgrade Project. This power upgrade requires updates to the RF system, superconducting LINAC, accumulator ring, and conventional facilities. The PPU will deliver 2.0MW to the existing SNS target and 0.8MW will be delivered to the future Second Target Station to facilitate new types of experiments and discoveries. The new power level fully applied to the existing target would allow the beam to damage the target and potentially produce hazardous radiation levels. To mitigate this risk, personnel protective system (PPS) called the Beam Power Limiting System (BPLS) has been designed to calculate the average and per pulse power, and to shut down the machine in the event of an excursion. Traditionally, PPS systems are implemented in programmable logic controllers designed to industrial safety standards. In order to quickly acquire measured data and calculate integrated power in real-time, a field programmable gate array (FPGA) was chosen to do the processing. The FPGA is implemented via off-the-shelf MTCA chassis and expansion boards. While MTCA has been applied in industry to life safety critical systems, the Beam Power Limiting System presented unique challenges and benefits when applying accelerator PPS design methodologies to MTCA technology.
To keep the MicroTCA standard viable over many years it must follow the development of technology. A PICMG working group was formed to incorporate faster Ethernet and PCIe communication into the standard. This talk will discuss the direction and challenges of the next generation MicroTCA standard.
After more than 15 years and the 3rd MCH generation being currently deployed, the next generation 4 MCH is will become available soon, providing new features and functions. N.A.T will explain how to transit from today’s MCH to the 4th generation MCH and what the differences and benefits are. Also, the new generation MCH is designed to meet the upcoming requirements addressed by the next generation of MicroTCA, providing more power, more bandwidth and higher bandwidth.
During last months PICMG mTCA-NG working group carried out channel signal-integrity simulations to find out whether 100GBASE-KR4 Ethernet and PCIe Gen4 and Gen5 are realizable on the mTCA platform. This presentation is intended to give an overview of the work carried out. The structure of the simulated channels and the models will be presented here. In addition, it will be shown how the evaluation of the AMC-/MCH-cards and backplanes will be carried out in the future with regard to signal integrity.
The FPGA Mezzanine Cards (FMCs) are commonly used in various industrial and scientific projects. FMCs are also often used as a modular extension of Advanced Mezzanine Cards (AMCs) in MicroTCA.4 systems.
PICMG (PCI Industrial Computer Manufacturers Group) standard organization is currently working on the extended specification supporting management of FMC modules in MicroTCA.4 systems.
Some of the FMCs available on the market could be complex and can consume a significant amount of power, that is dissipated in form of heat. Components on the modules can easily reach significant temperatures and therefore the devices require active cooling. MicroTCA.4 systems use temperature sensors available on AMC and RTM cards to monitor temperature and actively control fan speed in the chassis. However, there is no standardization for additional sensors, including thermometers, present on FMC modules.
FMC temperature sensors could be implemented as dynamic sensors that are read by the Module Management Controller (MMC) and allow monitoring of the health of the module as well as allow increasing the speed of chassis fans when necessary as it is done in MicroTCA.4. Currently, VITA 57 standard does not specify temperature sensors nor the I2C addresses for them.
The presentation discusses the possible solutions for various FMC sensors and extension of MicroTCA.4 intelligent platform management specification.
MTCA workshop for accelerator and physics in Japan 2021 was held from October 26-28 2021 in a virtual format. The goal of this workshop is to boost the application of MTCA in Japan by exchanging the information and experiences. The first day was dedicated for the tutorial session in Japanese and the other two days consisted of oral presentations. The workshop was very successful with more than 120 registered participants. The summary of the workshop and outlook are presented.
The 2nd MTCA/ATCA workshop in China has been held on-line in August when two years later of the first one. Summary of the workshop will be talked and the overview status of MicroTCA.4 development and applications will also be shown. Website of the workshp: https://indico.ihep.ac.cn/event/14765/
The Extremely Large Telescope (ELT) is under construction on Cerro Armazones in Chile. MicroTCA.4 will be used as a basis for the new modular ESO detector controller (NGCII) for all future visible and infrared scientific detectors. Specifically, IR CMOS detectors are the most commonly used detector type for the ELTs first generation of instruments. The presentation gives an insight into how commercial components and modules developed in-house are used to control infrared CMOS detectors and some of the challenges encountered while integrating MTCA.4.
Ground based astronomical observatories often require electrical equipment to reside out in the open air close to the telescope and instrument optics. The telescope and instrument optics are extremely sensitive to air currents caused by the warm electronics operating in domes open to the cool night air. In order to avoid these air currents the ANU in collaboration with ESO has undertaken to develop a MTCA.4 compliant conduction cooled image sensor controller capable of operating visible and infra-red CMOS detectors as well as CCDs for astronomical applications.
ESO are in the process of developing a MTCA.4 air cooled detector controller to replace the very successful ESO NGC. The conduction cooled MTCA.4 controller under development at the ANU will be highly compatible with the air cooled MTCA.4 system developed by ESO, allowing both systems to use the same AMC and RTM modules, thus ruling out the option of using the conduction cooled MTCA.3 system that is currently included in the MTCA standard.
We present a preliminary design for a 6 slot, 3RU water cooled housing capable of supporting six MTCA.4 modules enclosed within clamshells, along with the implications of this configuration on the high-speed backplane and the associated challenges.
The LLRF of the CERN SPS has gone through a complete renovation during the Long Shutdown 2019-2020. The upgrade was motivated by the High Luminosity LHC project (HL-LHC) that calls for the doubling of the SPS beam intensity .
Installation of two additional cavities and the obsolescence of the aging electronics required the redesign of the 200MHz cavity-controller system (RF feedback) and of the Beam-Control system (beam based loops). These new designs are now implemented on the MicroTCA platform.
The architecture of the SPS upgrade, the 200MHz cavity-controller and the timing receiver on MicroTCA will be presented.
The CERN Proton Synchrotron (PS) provides hadron beams to the downstream accelerators, to dedicated experimental areas and for anti-proton production. Six 200 MHz cavities are driven by a phase modulated RF signal resulting in controlled longitudinal emittance blow-up. The cavities also provide bunching for the PS-to-SPS transfer. During the long shutdown (LS2) an upgrade of the cavity controller has been carried out, and MicroTCA was chosen as the platform. The system consists of six SIS8300KU boards (Struck) on which the entire signal processing is implemented to generate the RF carrier synchronous with the beam. Each board is paired with a DS8MV1 rear transition module which provides ADCs for sensing the return signal from the cavities, as well as DACs and a mixer to generate the cavity drive signal at 200 MHz. To be synchronous with the circulating beam an AFC board (Creotech) receives the manchester encoded revolution frequency through a dedicated serial link, together with clock and data signals. These signals are then transferred to the cavity controllers on the SIS boards through the RF backplane (NAT) using the MLVDS lines. It also allows to distribute the White Rabbit synchronous clock and LO signals generated by a CERN custom made module. The system has been validated with beam and is now in the last development stages to operate all six cavity controllers in parallel and to complete the integration with the controls infrastructure.
MedAustron is a synchrotron-based particle therapy center located in Wiener Neustadt, Austria. The acceleration of the protons and heavy ions is achieved through a LINAC injector followed by a synchrotron, featuring three irradiation rooms for particle therapy and one room for non-clinical research. In the course of an ongoing development project, the LINAC LLRF will be upgraded to a state-of-the-art system. The MTCA.4 architecture which is envisioned for the upgrade is foreseen to be expanded for LINAC beam diagnostics and Synchrotron LLRF upgrades together with the RF knockout extraction system. This development project is being carried out through a collaboration between MedAustron and Instrumentation Technologies, combining the expertise and resources of both teams. Suitable commercial MTCA.4 components have been identified and evaluated against the requirements of the applications and the hard- and software system architecture of the aforementioned systems has been defined. This contribution describes the LLRF requirements, the proposed solution, selected MTCA.4 components used for the application and reports on the preliminary collaboration results.
At Helmholtz Zentrum Berlin (HZB), it is planned to apply mTCA.4 technology for the LLRF control of two of its accelerator facilities: BESSY-II and SeaLab. BESSY-II is a 3rd generation Synchrotron Light Source in operation since 1998 and focused on the generation of soft X-rays, complementing this way PETRA-III at DESY. It comprises a booster ring with one PETRA-type 500MHz normal conducting cavity and a storage ring with four High Order Mode (HOM) damped 500MHz cavities. In preparation of future upgrades and in order to make the injected bunches shorter, two more PETRA-type cavities have been introduced to the booster ring and are expected to start operation after the summer of 2022. mTCA.4 technology has been chosen to replace the old analogue LLRF systems as well as the development platform for the LLRF control of the recently introduced booster cavities.
A current project to study the possibility to upgrade BESSY-II is also ongoing: BESSY-Variable Pulse-Length Demo (VSR-Demo). The idea underlying VSR-Demo is introducing superconducting high harmonic cavities into the storage ring so different bunch lengths can exist in the storage ring simultaneously. At a first stage, a cryomodule with two 1.5GHz SRF cavities will be tested in the SeaLab bunker and will be controlled using mTCA.4 systems.
SeaLab (formely known as bERLinPro) for the moment incorporates a Superconducting RF Photoinjector module, a three superconducting two-cell cavity Booster module in the injector line and a Transverse Deflecting Cavity in the straight diagnostic line for bunch length and sliced emittance measurements. The mTCA equipment is distributed between powerful server CPU controlling Gun and 3 Booster instances and the TCav is distinguished into the standalone crate under AMC CPU control. The system is driven by precise Timing and synchronization system and has a Machine protection system on-board. Number of works are conducting to ensure the project commissioning planned for year 2022.
Finally, HZB also operates the Metrology Light Source (MLS) owned by the Physikalisch Technische Bundesanstalt (PTB) where it is also planned to upgrade its old analogue LLRF system using mTCA.4.
A new Zone 3 Class RF1.0 was first announced on the MTCA WS in 2018. The preliminary specification of the Class RF1.0 was presented in 2019. Maesurements with signal frequencies of up to 3 GHz indicated a high potential of the used connectors.
Now the first AMC - RTM comnbination with the Class RF1.0 has been built to test the RF performance of the CLass RF1.0. A new custom SMD footprint for the Coaxi Pack 2 connector further improves signal integrity and significantly reduces intra-insert cross-talk.
First performancce measurement results on the reference AMC - RTM combination and a more detailed specification of the Zone 3 Class RF1.0 will be presented.
The DeRTM-LOG1300, a MicroTCA.4 compliant LO and CLK generation module, has been successfully in operation at XFEL and FLASH for several years. With the company KVG Quartz Crystal Technology GmbH we started a collaboration in order to produce additional LO and CLK modules. At the same time, other machines require different LO and CLK frequencies. Not all of these frequency requirements can be covered with the present architecture. In the presentation we give a short overview of the current status and consider other possible LO and CLK generation techniques to provide frequencies required by other machines with different reference frequencies. In the second part of the contribution the KVG Quartz Crystal Technology GmbH will give a short overview of their activities.
At the ELBE accelerator center a new timing system is being developed based on the MRF hardware platform. It uses two mTCA-EVM-300 configured as masters and a scalable number of connected receivers (mTCA-EVR-300U, PCIe-EVR-300) to generate flexible pulse patterns for operating the machine. It allows for independent operation of two electron injectors and offers the opportunity for a combined injection into ELBE.
The control software is tailored to ELBE’s requirements based on mrfioc2. All machine operations modes as well as plausibility checks have been implemented. The communication interface to the ELBE control system is provided by a Siemens PLC that is at the same time integral part of the machine safety system. It sets the allowed parameter space for the timing system according to the current machine state and interlock signals.
The system will provide timing signals on few picosecond level to machine subsystems as LLRF and diagnostics as well as to user labs allowing for individual trigger generation based on the machine event signals. Universal IO modules offer a variety of logic levels on the receiver front panel while the MicroTCA backplane can be used to trigger hardware installed.
The Super Proton Synchrotron (SPS) Low-level RF (LLRF) system at CERN was completely revamped in 2020. In the old system, the digital signal processing was clocked by a submultiple of the RF. The new system uses a fixed-frequency clock derived from White Rabbit. This triggered the development of an eRTM module for generating very precise clock signals to be fed to the RF backplane in MTCA.4 crates. The eRTM14/15 sandwich of modules implements a WR node delivering clock signals with a jitter below 100 fs. This presentation will explain the general architecture of this new LLRF system, highlighting the role of the eRTM14/15 module and the LLRF backplane.
At DESY we are in the technical design phase for the upgrade of the PETRA III synchrotron light source towards a 4th generation low emittance machine PETRA IV.
Within this major machine upgrade also almost every electronics for the accelerator controls will be renewed. As the Platform of choice MTCA.4 shall become the new standard.
Because of the good experience with the DESY developed MTCA.4 based timing system from the European XFEL, we decided to reinvent the well-established timing system of PETRA III and its pre-accelerator chain on this base to fulfill the enhanced requirements for PETRA IV. Therefore, the system design and the development of a successor AMC card for PETRA IV is currently in progress.
In the presentation we will show the requirements for the PETRA IV timing system and first concept for its major component, an AMC card named X3Timer. Further on we will present the currently running pre-tests and the state of the hardware development.
The Spallation Neutron Source (SNS) employs a custom Timing System for synchronization of the accelerator and target systems. The variable frequency design of the SNS Accelerator requires the custom system and presents several unique design challenges. The core component of the SNS Timing System are the two sets of data links that are provided to end user systems, the Event Link(EL) and Real Time Data Link(RTDL). Any timing receiver used at SNS must support receiving and decoding these bi-phase mark encoded links. The original end user timing receivers were VME or PC based but modernization efforts at SNS are being completed using MicroTCA systems. As migration to MicroTCA for various systems and future upgrades timing was an integral requirement for these systems. To minimize custom designs and development time the choice was made to use a MicroTCA FMC carrier card from a commercial vendor with a custom design on an FMC form factor for the timing receiver. The carrier card handles the programmable logic which simplifies the FMC. This facilitated quick design and deployment for multiple systems. Three Timing Receiver FMCs have been developed to support different applications at SNS. Currently these are used in production for Ring LLRF, Machine Protection, and Injection Kicker Power Supplies. Future plans include support for the SNS Proton Power Upgrade Project(PPU) for the LINAC LLRF, Beam Power Limiting System(BPLS), and HPRF as well as further modernization efforts throughout the facility in the next 10 years.
The Hefei Advanced Light Facility (HALF) is a fourth-generation vacuum ultraviolet (VUV) and X-ray diffraction limit synchrotron radiation (DLSR) light source now under preliminary research. To achieve ultralow beam emittance and small beam size, the orbit of the beam in DLSR storage ring should meet the stability requirement at submicron scale. The beam position monitor (BPM) electronics measures the orbit and is hence an essential part of the beam orbit control system. We design a BPM electronics based on the MicroTCA.4 standards platform, which consists of an MicroTCA.4 module (including a chassis, a power supply, and a digital board, etc.), a customized RF front end module, and a frequency synthesizer. IQ sampling and digital signal processing algorithms are implemented to obtain turn-by-turn (TBT) data, fast acquisition (FA) data at a 10kHz rate, and slow acquisition (SA) data at a 10Hz rate. To evaluate the performance and function of BPM electronics, we conducted offline tests in the laboratory and beam tests based on the storage ring of HLS II, a light source similar to the HALF as an alternative. Test results indicate that the performance of MicroTCA.4-based BPM electronics can meet the requirements of the HALF storage ring.
Powerful hardware boards are key components for future installations at DESY and other facilities. To complete the portfolio, three new AMC were projected. All new cards base on the XILINX MPSoC FPGAs which provide an exceptionally convenient way for user application development, integration and maintenance - allowing the use of high-level programming languages such as Python or SystemC.
The most advanced new board is the DAMC-DS812ZUP. It is the first product of the new coaxial analog Zone 3 RF Class. Using the new interface, 8 analog channels can be transferred from front or rear input and captured by low-latency 12-bit digitizes with 500 or 800 Msps sample rate. The ADCs feature 2.7 GHz analog input bandwidth; the amplifiers have a bandwidth of 4.8 GHz, so that the card can also operate in an interleaving mode with 1600 Gsps data rate.
In addition, DESY has been developing a MicroTCA.4-based mutlti-axis motion controller: DAMC-MOTCTRL. This board is a contribution to the ecosystem, since it enables controlling motion in big experiments from within the MicroTCA crate. It is designed to move up to 48 stepper motors per card in parallel - which means each card replaces up to 6 VME cards. One major benefit is the possibility to aggregate multiple cards inside crate and across DESY campus. This allows to perform position-synchronous data acquisition. Using the MicroTCA features, this device can interact with virtually any other MicroTCA card and trigger user-programmable actions.
To open the door towards new serial JESD204 digitizes, a new AMC card is also under development. It will come with RTM Class D1.2 and Class D1.3 assembly options and with high-bandwidth LVDS and MGT Zone3 interfaces so that especially new serial converters with many parallel MGT lanes can be integrated on the RTM.
A powerful MPSoC Chip is used on the AMC, so that the application can benefit from high-bandwidth parallel memory interfaces and a large number of optical transceivers on the front panel.
In the past year, ChimeraTK's DeviceAccess library has seen some major improvements. A new backend is available for the Xilinx XDMA PCI express driver. This brings direct support for all recent Xilinx FPGAs, not only for data I/O but also for PCI express user interrupts. The latter was possible by introducing support for push-type variables to all built-in backends, which means a processing thread can wait for new data instead of actively polling the device.
The combination of ChimeraTK's DeviceAccess, ApplicationCore and the ControlSystemAdapter allows to write device applications which seamlessly integrate into various control systems. Just by configuration, without changing a single line of C++ code, devices based on ChimeraTK can be used at different facilities. This makes ChimeraTK an ideal tool to foster collaborations which are beneficial for hardware vendors, application programmers and end users of the MicroTCA platform.
The Module Management Controller (MMC) is a mandatory component of every AMC board. DESY is developing, maintaining and licensing a turn-key MMC solution that is used on several hundred boards in different facilities - on DESY's own products as well as on third-party AMC boards developed by industrial customers and project partners.
With the growing number of different boards, a clear separation between common code shared across boards and board-specific code becomes crucial - to keep the codebase maintainable as well as to provide a high-level API for AMC board developers who should be able to focus on their application without having to care about the low-level workings of the MMC. The high-level API makes a software development kit (SDK) possible, which is offered to MMC Stamp System-on-Module customers who wish to customize the pre-programmed firmware according to their needs. This presentation gives a brief overview of the SDK and the high-level API it provides to AMC board developers.
The MicroTCA is a key platform at the European X-Ray Free Electron Laser facility (European XFEL), being at the centre of timing distribution, data processing from large 2D detectors, fast digitization and processing of pulse signals as well as low latency communication protocol for VETO and Machine Protection Systems.
Following on our internal review from last year, we focus on integrating new MicroTCA based solutions into our facility to address current and future challenges. We continue to work on our FPGA development workflow, evaluating different verification methodologies. Finally, we have started looking into Machine Learning with FPGA as the base platform.
The Lodz University of Technology, Department of Microelectronics and Computer Science is involved in the development of MicroTCA.4, MicroTCA.4.1 and the future standards from 2007 onwards. Since that time, we have developed various MicroTCA.4 components including Intelligent Platform Management, Advanced Mezzanine Cards (AMCs), Rear Transition Modules (RTMs) for data acquisition and processing systems used in numerous accelerators and fusion projects.
The presentation discusses selected projects currently performed at our department based on the MicroTCA.4 technology.
Firstly, a scalable framework supporting various camera standards based on the MicroTCA.4 technology will be shown as an example of a powerful image acquisition and processing system dedicated for large-scale physics projects, such as ITER, Wendelstein 7-X or Eu-XFEL.
Secondly, the extension of the IPMI specification and further support for FMC modules based on the developed prototype are discussed and a smart MMC solution is demonstrated on the example of a cost-effective but efficient AMC module that we have developed for the W7-X stellarator.
Finally, the progress of developing the high-power piezo driver (HPD-200) for the European Spallation Source (ESS) accelerator will be presented as an instance of enormous challenge breaking the limitations of the MicroTCA specification.
Universal, scalable image acquisition system based on MTCA.4 standard designed and developed by the Department of Microelectronics and Computer Science in Lodz University of Technology is constantly being expanded with support for new cameras and interfaces. For more than 10 years we have been collaborating with several research institutions like ITER, W7X, DESY to collect requirements and provide various imaging systems for diagnostic purposes. Currently, the system supports various camera interfaces (Camera Link, Camera Link HS, GigE Vision) and was integrated and tested with various cameras from different manufacturers.
A growing portfolio of supported devices and significant differences between camera interfaces made the previous software insufficient and difficult to maintain. Therefore, it became increasingly important to create a universal software framework easily expandable and maintainable, able to handle the growing needs for support of new devices - cameras and frame grabbers. The framework, unified from the user point of view, needs to support various frame grabber modules with different interfaces and a wide range of cameras communicating over numerous protocols.
To avoid creating a new homemade standard, the framework is based on the GenICam. It is a common standard developed by leading manufacturers of imaging equipment that provides unified API and clear hardware abstraction layer. The MTCA.4 image acquisition module is integrated with GenICam-based software stuck by providing an appropriate GenICam Transport Layer (GenTL) library. Various cameras with Camera Link interface are supported by providing dedicated CLProtocol libraries. Finally, all the hardware components can be used in a unified way using the common GenAPI interface offered by the GenICam standard.
The software framework includes also console and GUI tools for device control and image acquisition written in C/C++ and Python. Provided software components supporting 3 different cameras have also been successfully integrated with the Java-based control environment of W7-X stellarator using standard GenICam wrapper.
In my presentation I will give an overview of MTCA hardware, which is relevant for photon science experiments. I will show commercially available products and new developments including the new motion controller. By showing possible applications for PETRA-IV I will point out the advantages of MTCA.
The Mu2e experiment, currently under construction at Fermilab, will use a pulsed beam structure to significantly improve limits on the rates of charged lepton flavor violating muon decay processes. The time structure of the pulsed beam is measured by the extinction monitor, comprised of scintillation counters and a silicon pixel detector telescope, which are read out using a data acquisition system made from commercial MicroTCA components. We describe this data acquisition system, the decision to use MicroTCA in its implementation, the constraints imposed by the MTCA.4 standards, and the ways in which the hardware features available in commercial components have been integrated into the design.
GSI is a particle physics research institute located in Darmstadt, Germany. At the same location, a new accelerator facility called FAIR (Facility for Antiproton and Ion Research) is currently under construction.
We are using MicroTCA systems for measuring beam parameters like position, intensity and profile, for accurate timing control, for measuring voltages and for control applications.
The MicroTCA devices currently in use will be presented as well as some selected experiences and problem solutions.
In todays advanced and digital world traditional analog signal acquisition and processing are gradually shifting to digital domain to meet the needs of the hour. In the field of energy dispersive x-rays detectors traditional analog signal processing involves a pre-amplifier to amplify the signal, a shaping amplifier to detect the energy of the incident photon, and a multichannel analyzer (MCA) to generate the energy spectrum.
The use of digital signal processing allows to enhance the system, achieve more flexibility, reduced noise by adding advanced digital and faster data processing methods, which will enable higher counting rates above million counts per second.
With digital signal processing the output of the preamplifier is digitized and all further processing is done in a field programmable gate array (FPGA).
Currently available devices in the market perform the signal processing step either in digital signal processors (DSPs) or FPGAs. Most of these devices such as the Struck SIS3302 use trapezoidal filtering, which gives good energy resolution at large shaping times.
In our presentation, we will show different algorithms for data preprocessing, shaping and postprocessing. We will show that by preprocessing the data, we can get better energy resolution at shorter shaping times; thus, it will allow good energy and time resolution at high count rates. To enhance the quality of signal, signal preprocessing methods such as moving average filter, savitzky-golay filter and others will be shown. For signal shaping, methods such as trapezoidal filter, triangular filter and postprocessing methods such as deconvolution will also be demonstrated. The results of the filters will be compared by applying them to identical experimental raw data. Based on theoretical and experimental results an analytical comparison of the methods will be carried out for the implementation.
With the current upgrade to W7-X, an actively-cooled divertor will be installed. This necessitates a sophisticated protection system, to ensure that the internal components of the machine do not overheat. The key DAQ components are high-fidelity infrared and optical cameras. This system alone will consist of more than two dozen cameras with multiple GBit/s data rates each and the requirement for real-time processing. This makes mTCA an ideal environment to develop a single infrastructure to accommodate all the different camera types. Taking a broader approach, the aim was to create a generic framework which can integrate different camera hardware standards (CameraLink, CameraLink HS and others) and all cameras which are GenICam compliant. This talk will give an overview of the architecture and present the initial results obtained for the whole chain (Camera to W7-X data archive).
In order to minimize the latency of Sirius Fast Orbit Feedback (FOFB), a 12-channel current source power supply was designed as a μRTM module. Each channel consists of a linear amplifier operating as current source by means of a digital feedback loop implemented on an FPGA at the AMC board. The amplifier is specified to reach up to 10 kHz small-signal bandwidth on a 3.5 mH inductance magnet and ±1 A full scale. This work will report on the performance figures obtained prior to releasing the design for final production.
In the scope of the TDR phase for the future PETRA IV low-emittance ring upgrade project, special attention is being dedicated to the prototyping of the future BPM electronics. The large machine will use a large number of BPM pickups, around 800, and the requirements for each system will be stringent for what regards resolution, accuracy and long-term stability. To acquire and process all the signals from the Beam Position Monitors of each cell, a MTCA.4 system with 6 RF BPM modules is being prototyped by DESY and Instrumentation Technologies. Each BPM module consists of RTM and AMC cards and will sample the signals from 2 BPM pickups, with a total of 8 input channels per RTM card. The RF cables will vary in length from BPM to BPM and will be exposed to a non-controlled temperature environment. To fulfill the strict long-term stability requirements, a cross-bar switching matrix will be used. The matrix will be installed in the tunnel next to the BPM pickup and will be remotely controlled by the MTCA.4 platform’s BPM modules. The real-time digital signal processing is then able to compensate the disturbances and drifts along the cables. This contribution presents the BPM prototype, focusing on the signal processing applied from the BPM pickups until their acquisition and digitization on the application-specific RTM modules, and further processing in the FPGA of the AMC module. Preliminary results will be presented as well.
BESSY II operates with special fill patterns that include transversely moving bunches, which should be ignored in the calculation of the beam postion. To enable this, a system of four 1 GS/s ADCs is used to acuire the button amplitudes with the required fidelity. This talk will present the status of our plans, including aspects of MTCA crate, ADC and FPGA selections, as well as sample clock distribution. Integration into a future Orbit Feedback System will also be briefly discussed.
BPM electronics at SOLEIL also embed the FOFB communication and computation.
As these electronics come to an obsolescence, we aim at a new orbit feedback system.
A dedicated standalone microTCA based platform is envisioned for this new system. This new architecture composed of cell and central nodes will (among other tasks) collects the BPM data, computes and send to the correctors the appropriate settings to correct the beam orbit.
In this speedtalk, we'll present the planned architecture, the considered equipments and the first tests to validate these choices.