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The 12th MicroTCA Workshop for Industry and Research will take place from 5-7 December 2023 at DESY.
The main topics of the workshop are:
The industrial exhibition will be open at the following times:
The registration fee is
• AMC, MicroTCA: the form factors
• available systems (cooling, backplanes,
slots, MLVDS bus, …)
Useful tools and commands
Modernizing the Fermilab accelerator control system is essential to future operations of the laboratory's accelerator complex. The existing control system has evolved over four decades and uses hardware that is no longer available. The Accelerator Controls Operations Research Network (ACORN) Project will modernize the control system and replace end-of-life power supplies to enable future accelerator complex operations with megawatt particle beams. The ACORN project is planning to replace Fermilab’s obsolete CAMAC crate-and-card controls hardware with modern MicroTCA hardware. There are over 2,000 CAMAC cards and over 250 CAMAC crates serving various functions in Fermilab’s control system. We will present an overview of the existing CAMAC hardware and the proposed MicroTCA replacement plan.
With over 300 MicroTCA systems to be deployed at ESS covering multiple applications, how they are setup and maintained is an important consideration.
This talk will give an overview of where the MicroTCA systems are being installed and how ESS is applying automated scripts and playbooks to ensure a standard deployment that is easy to use and maintain.
The LLRF systems based on MTCA.4 in Japan Proton Accelerator Research Complex (J-PARC) are working stably and reliably. They support the stable beam delivery from RCS and MR to the experiments at very high beam power. There are several MTCA application projects at J-PARC, for example, timing modules and a new feedback system against beam instabilities. A COTS MTCA digitizer is now utilized for beam signal acquisition. The status and future plans of the MTCA applications at J-PARC are presented.
In the framework of the High Luminosity LHC project (HL-LHC), crab cavities (CC) will be installed on both sides of the LHC interaction point (IP) 1 (ATLAS experiment) and point 5 (CMS experiment) to restore an effective head-on collision and minimize the geometric luminosity loss which arises from the crossing angle. Two crab cavities will be installed on each side of the IPs for each beam for a total of sixteen cavities.
The stringent requirements of the low level RF (LLRF) for crab cavities will be briefly described. The architecture of the LLRF system will be presented, it will be based on the MicroTCA platform and the use of a digital deterministic link for RF synchronization (the so-called White Rabbit). The project foresees the development of a new eRTM module and will benefit from the SPS LLRF upgrade put in operation in 2021.
The CERN Super Proton Synchrotron (SPS) Low Level RF system has been entirely renewed using the MicroTCA platform. It is in operation since 2021, to provide beams for the Large Hadron Collider (LHC) and experimental areas. The cavity controllers and beam control are implemented mostly using commercially available components, while a White Rabbit synchronous clock and LO generator was designed in-house. A modular approach based on a MPSoC FMC carrier enables the utilization of 5 Gsps and 125 Msps ADCs for the various beam pick-ups of the beam control. Most of the MicroTCA.4 features are leveraged for controls, data acquisition (PCIe), point-to-point 10 Gbps links and clock distribution. In this presentation we will go through the system architecture and hardware, the commissioning results and the overall experience with the new platform.
Synchrotron SOLEIL has elected MTCA as a platform standard baseline for its future or renewed systems. Indeed, multiple upgrades are foreseen as the facility will upgrade to SOLEIL II, a 4th generation synchrotron light source. In this presentation, we focus on two ongoing projects based on MTCA platforms: low level RF and fast orbit feedback, by presenting the technology choices, developments, installation and first results. The administration tools of MTCA systems, notably through Zabbix, will be presented.
The global strategy of MTCA integration to SOLEIL control system will also be outlined, with a focus on the development of a connector to adapt Tango Control system to ChimeraTK framework which is used to access to MTCA based systems.
The superconducting stellarator W7-X underwent a major overhaul between 2018-2022 with the installation of an actively-cooled divertor and inner wall. The CoDaC System also received a significant overhaul and expansion. The protection of the new divertor required substantial enhancement of the Fast Interlock System, which necessitated a new hardware infrastructure and new implementation. The real-time system had to be ported from the existing VXworks implementation to a real-time linux, in order to accommodate the new divertor protection system. In addition to work on the central components of CoDaC, around 15 completely new diagnostic systems were implemented and another 20 were significantly enhanced. This included a new mTCA-based camera acquisition framework with now enables all cameras at W7-X (which includes CameraLink, CameraLink HS and GigEVision) to run on the same hardware platform with minimal adaption of the software.
As W7-X is geared towards steady-state operation, all data has to be streamed to the archive and cannot be stored locally and uploaded at a later time. The addition of >24 high-speed cameras required a substantial upgrade of the network streaming capacity and the central storage. In order to reduce the requirements as much as possible, a real-time lossless compression algorithm has been implemented for camera data, which was adapted to the W7-X environment yielding a >60% compression rate.
This paper will provide an overview of the changes and upgrades of the W7-X CoDaC system from 2018-2022 and show results from the OP 2.1 campaign with special emphasis on the newly introduced mTCA-based systems and the ones currently under development.
The primary goal of the Machine Protection System at the Spallation Neutron Source is to shutoff beam in under 20usec for any adverse condition that could affect or damage the beamline systems. The MPS at SNS is based on the original design that was completed in 2001 and has been obsolete for many years and requires an upgrade. The upgrade path for all new control systems in the Accelerator Division is to utilize MicroTCA were applicable. The new MPS is using MicroTCA for all components including MPS Master, Node Processors, Trigger Control, and end Field Nodes. The new system is undergoing final deployment currently and has been through preliminary testing. The new system must perform all functions and meet requirements as good or better than the legacy system and be fully functional and deployed by mid-2024.
10 years have passed since the first LLRF systems based on the MicroTCA standard were installed at DESY. This contribution provides an overview on the different installations, their configurations, and how the modularity of MTCA systems was exploited to realize different LLRF architectures using similar blocks. Return on experience with these systems will be presented.
This is to report the 2023 MicroTCA/ATCA for Large Scientific Facility Control Workshop held in Shenzhen, China from October 31 to November 2. The workshop resumed the trend of annual MicroTCA meeting in China which was interrupted due to the Covid-19. There were over 84 participants registered and 35 talks presented in the workshop. Leaders of IASF and the Shenzhen FEL project's high-level executives participated in the workshop. The workshop introduced the latest achievements of MicroTCA at Desy, as well as many successful application cases in China. Participants also discussed about the future development of MicroTCA in China. Overall it was a very successful meeting to move forward the MicroTCA activities in China.
To keep the MicroTCA standard alive it has to follow major developments of technology. The most prominent progress is the increasing transmission speed of CPUs and FPGAs. And on the application side the increasing sizes of image sensors together with increasing update rates for example require much higher system throughput. To address these needs the MicroTCA Next Generation working group of PICMG has recently released version 3 of MTCA.0 that provides the prerequisites for a factor of four speed improvement. The presentation will also cover the further planned steps to enhance the MicroTCA standard.
PICMG is a nonprofit global consortium of companies and organizations that collaboratively develop open standards for high-performance embedded computing applications, including MicroTCA which released a new revision in 2023. This presentation will survey the 29 years of open specifications and introduce our new initiatives. We will discuss the current specifications, our development processes, and the value of PICMG membership.
PICMG members benefit by participating in standards development, gaining early access to critical technology, and developing relationships with thought leaders and suppliers in the industry. The consortium’s work product influence and mission critical applications to thrive for decades.
Each application is different and therefore needs some tweaks to the used hardware to adapt to the customers’ requirements. This talk gives an overview about the nVent SCHROFF Standard MTCA.4 crates and how they are built on standard building blocks to easily adapt the crates to the application and customer requirements.
A few samples of custom specific crates will be presented and how they are designed based on the nVent SCHROFF standard Crates and standard building blocks.
Based on an existing RF-SoC system, powerBridge is developing an MTCA FPGA Board based on an RFSOC FPGA. Due to the high ADC (10 Gsps) and DAC (5 Gsps) this board will fit for application of signal generation, SDR, Quantum Computing, etc.
In combination with optional Front Ends there is the possibility of pre filtering and amplifying the signals.
Since the beginning in 2006 MTCA has often been looked at as being complex and loaded with some overhead. In the past, attempts have been made for smaller and more cost sensitive solutions to provide new user groups with an efficient platform to prove the advantages of MTCA as an embedded standard for different applications and market segments.
During the last 2 years N.A.T. spent a significant amount of time with customers in various market segments including research and commercial markets to develop a MTCA platform that efficiently combines the different market requirements but also provides sufficient flexibility for other customers to engage with this open standard.
In this presentation we will explain how a small MTCA system with full MTCA capability and function still provides sufficient space for additional payload boards while supporting high bandwidth at the backplane and delivers efficient uplink functionality to external systems.
In addition to its effectiveness, this MTCA-server is supposed to also meet special requirements regarding timing and synchronization.
The advent of MicroTCA (MTCA) systems has revolutionized the landscape of embedded computing, providing a robust platform for a variety of high-performance applications. In the realms of quantum computing and advanced medical diagnostics, the demand for high-speed data transfer and precise imaging is paramount.
This talk delves into the integration of CoaXPress (CXP) camera link technology within MTCA systems, a synergy that offers a leap in performance and reliability.
I-Tech and DESY have developed a MTCA.4 BPM electronics prototype for Petra IV TDR, which consists of the BPM-optimized signal conditioning RTM module from I-Tech, and the DAMC-FMC2ZUP AMC processing board from DESY MSK.
While the DAMC-FMC2ZUP board proved to be invaluable for the prototype phase, it is an overkill in terms of the FPGA resources required for the BPM application. In light of the cost optimization of the final ~800 BPM series for Petra IV, a new DAMC-UNIZUP universal processing AMC board has been developed by DESY MSK, featuring a range of smaller Zynq Ultrascale+ SoC, D1.2 and/or D1.3 Zone3 standard, as well as full bandwidth availability for the LVDS lines to/from the Zone3 connector. The new board features are discussed in light of the current BPM, as well as future potential applications.
Short introduction to EMCOMO and Vadatech, the major benefits of the brand new standard MicroTCA.0 R.3 and upcoming new products from Vadatech.
After almost 18 years of successful deployments, the 3rd generation of NAT-MCH is getting closer to its end of life, while the 4th generation of NAT-MCH is available now.
The 4th generation is MTCA.0 Rev 3 compliant and has been designed to meet the upcoming requirements addressed by the next generation of MicroTCA as close as possible already.
It provides a lot of improvements and new features and functions, such as 10GbE base switch with 25GbE uplinks, new 40/100GbE fat pipe hub with 10/40/100GbE uplinks, new PCIe Gen 4 fat hub, new CLK module with replacement for IDT multiplexer, new web and harmonized CLI interface in order to name a few.
After a short introduction to new features and how new and existing customers can benefit from these, N.A.T will explain how existing customers for the 3rd generation of NAT-MCH can easily migrate to the 4th generation MCH in existing applications.
As part of the proposed AWAKE run 2c upgrade, an additional electron injector will be installed to produce a 160 MeV electron beam. The injector consists of an S-band photoinjector, an X-band buncher and a pair of high-gradient X-band accelerator structures. RF pulse compressors are required to reach the design energy, adding complexity to the LLRF control system. A MicroTCA based LLRF system using the Struck SIS8300-KU digitizer AMCs and DWC8VM1 RTMs has been used to develop a prototype LLRF system at Uppsala University using the DESY Board support package. The LLRF system, which was initially developed at Uppsala University, has been relocated to CERN. The goal is to integrate it into the CERN control infrastructure based on the FESA (Front-End Software Architecture) platform. The talk will present an overview of the project and current progress.
For 30 years, the ASDEX Upgrade diagnostics provided scientists with the experimental data needed to advance the field of fusion. During this time, the machine's systems and diagnostics have evolved. In-house production of state-of-the-art data acquisition hardware has been the norm. However, the serial input/output standards SIO1, SIO1a, and SIO2 have reached the end of their useful life. While it is still possible to maintain existing hardware, it is no longer feasible to produce new boards. The goal is to make the transition to the MTCA hardware standard as painless as possible. Much of the front-end electronics application-specific boards are housed in PIPE crates, such as the magnetic field integrators. These integrator channels are very expensive and replacing them is not efficient. A step-by-step approach is presented that is applied on three fronts: new diagnostics, old front-ends, and a new software framework. New diagnostics should be made available as soon as possible with MTCA-compatible technologies. These diagnostics use D-TACQ ELF modules, which in the future can be integrated into an MTCA crate using DESY AMCs and a d-tacq RTM. The PIPE crates are controlled by a slot-in interface card that supports the old standard. However, the new interfaces should use standard protocols such as PCIe or 10G Ethernet. These technologies will allow the front-ends to be upgraded or connected to MTCA in the future. To update the diagnostic software framework, ITER and DESY standards are considered. The concept uses EPICS as configuration and monitoring layer. This is connected to ITER NDSv3 drivers that standardize the device access so that any AUG diagnostics can be controlled in the same way. The DESY FPGA Framework (FWK), which supports future DESY AMCs and device access layer, completes the vertical integration plans. It is of utmost importance to find a standard solution. Current estimates count the old front-end channels in more than 7000, divided into more than 60 diagnostics. The work is in the conceptual phase, and ideas and diagrams are shared for discussion within the MTCA community.
GSI is a particle physics research institute located in Darmstadt, Germany. At the same location, a new accelerator facility called FAIR (Facility for Antiproton and Ion Research) is currently under construction.
Our beam instrumentation department is using MicroTCA systems for measuring beam parameters like position, intensity and profile, for accurate timing control, for measuring voltages and for control applications.
The presentation will handle recent MicroTCA related topics:
* A custom µTCA RTM has been developed using KiCad for connecting to precise current measurement devices used together with ionization chambers
* (Our solution for flashing FPGA gatewares via PCIe might be presented as well)
The Universität Hamburg, in collaboration with DESY, is developing an electrical ground-support equipment phasemeter, or phasemeter simulator, based on the MicroTCA.4.1 standard, for the space-based gravitational-wave detector LISA, funded by the German Aerospace Agency (DLR). The main task of the phasemeter is to extract the phase of various laser interferometer beat note signals with microcycle precision at frequencies between 0.1 mHz and 1 Hz. Additional functions include the readout and generation of ranging and data communication sidebands, frequency control of the lasers and signal acquisition. The development is conducted in parallel to, and in collaboration with, the development of the flight hardware phasemeter and the simulator will be made available to the partners within the LISA consortium for the assembly, integration, verification and testing (AIVT) phase of the mission and for the technology development of payload items.
We present the system design, the phasemeter software for controlling and data acquisition and the status of our hardware development.
In this talk, we will present our latest developments, such as our universal MPSoC-based RTM connectivity board (DAMC-UNIZUP), our 8-channel SFP+ RTM fanout board (DRTM-8SFP+) or the DAMC-DS5014DR, our RFSoC-based digitizer that is currently under development.
We will show measurements of the Yamaichi AMC connector and we will give an update on our MicroTCA Motion Controller (DAMC-MOTCTRL). Finally, we will present all the lab tools and design templates that we have created over the last years to support the MicroTCA community.
MTCA-based systems are widely used at many of DESY's accelerator facilities. A brief review of the current accelerator controls status and some experiences with focus on the used MTCA technology will be shared. After the successful implementation of MTCA at the European XFEL and FLASH facilities meanwhile this hardware standard and platform made its inroads into the various new projects and accelerator research and development programs at DESY. A short overview of these and related projects at DESY will be presented.
Although MTCA is already well established for accelerator control systems, its use at synchrotron beamlines is still a novelty. DESY is currently planning to adopt the MTCA standard for experiment control and data acquisition at the new synchrotron radiation source PETRA IV.
In my talk I will present potential applications of MTCA in photon science. I will particularly highlight two important projects at DESY: The development of a MTCA based motion controller and a data acquisition system for energy dispersive detectors.
Within the framework of the first phase of MYRRHA (Multi-purpose hYbrid Research Reactor for High-tech Applications) project, called MINERVA, IJCLab was in charge of a fully equipped Spoke cryomodule prototype development, to be tested at 2K. It integrates two superconducting single spoke cavities, the RF power couplers and the Cold Tuning Systems associated.
On the control side, a MTCA.4-based Low Level Radio Frequency (LLRF) system prototype and the Software/EPICS developments has been realized by IJCLab and SCK CEN in collaboration with IOxOS Technologies. The final version of the global system and the results of the tests at 2K will be shown with some perspectives for the future.
OpenMMC is an Open Source MMC firmware for MicroTCA AMCs. It currently
powers the AMC FMC Carrier (AFC) versions 3.1 and 4.0. Several
improvements have been made to the code over the last year to address
some shortcomings of previous releases, like removing redundant code,
add HPM compatiblity with ipmitool, replace hard-coded clock mux
setting with configuration over IPMI.
An extensive road-map for version 2.0 has been put in place to guide
future development envisioning better modularity, ease porting to
other boards / microcontrollers and better error handling.
This presentation gives an update on the new modular astronomical detector controller (NGCII) developed at ESO. The controller will be used for all future instruments on the Extremely Large Telescope (ELT).
In 2023 laboratory first-light has been achieved with two different CMOS detectors. CMOS detector related MTCA hardware is in the process of being readied for series production by fixing issues encountered with the prototypes and developing an automated test and calibration setup.
In parallel, preparations are ongoing for first light with a CCD detector. For this, another set of MTCA.4 modules, including a clock module using direct digital synthesis (DDS) to generate arbitrary clock waveforms, are developed.
Atom Computing continues to expand its usage of the MicroTCA platform to control its next generation of quantum computers. In this talk, we will present a brief overview of Atom Computing and how we are using MicroTCA to implement the control system for our neutral atom based quantum computer.
We will then touch upon our experience using MicroTCA as we have expanded the usage of our control system to more quantum computers. As our computers and teams span across many sites, we discuss our development and installation timeline and our experience with remote maintenance and uptime.
Additionally, we will discuss how we use the MicroTCA platform to enable certain applications within our current control system. We then conclude with some thoughts on the requirements for our next generation control system and how the MicroTCA platform may be used to enable these features.
KVG Quartz Crystal Technology GmbH is a professional frequency control products manufacturer, focusing on research, development, production and sales. High-end crystal oscillators are our specialty. We cooperate with DESY for the production and test of the Master Oscillator (MO) module and the DeRTM-LOG modul. The MO module can provide different fixed frequencies with excellent short-term noise below 1fs and long-term stability and high-power output. Besides, diagnostic units for various functions are available. The DeRTM-LOG is a MicroTCA.4 compliant and a multi-channel low noise local oscillator generator and high frequency signal and clock distribution module. Currently the DeRTM-LOG 1.3GHz and DeRTM-LOG 1.5GHz are available.
HEPS-BPIX40 is an new hybrid pixel detector developed for the High Energy Photon Source in China. This detector represents a significant advancement from its predecessor, BPIX20, boasting a larger 128 x 96 pixel matrix and smaller 140 μm x 140 μm pixel size. The circuitry of HEPS-BPIX40 operates in single photon counting mode, incorporating dual thresholds and programmable gains for enhanced performance.
In terms of frame rate, the detector module has been tested to achieve up to 2 kHz in continuous readout mode. Each detector module covers an area of 3.7 cm x 8.1 cm and comprises 2 x 6 chips. To accommodate the full system, which will consist of approximately six million pixels distributed across 40 modules, four MicroTCA crates are employed for continuous data readout. The estimated maximum data rate will reach 165 Gbps at 1 kHz frame rate, which poses a significant challenge for both the backend electronics and the data acquisition system. In addition, the White Rabbit (WR) is adopted for system-level clock synchronization.
Currently, preliminary tests have verified the module and chip design. X-ray imaging results have been obtained by a module (uncalibrated). More detailed results for the full system design will be presented in this talk.
Next gen of AMD Controller and Processor cores
In recent years, DESY has diligently developed an open-source FPGA framework, known as FWK, aimed at expediting FPGA development within the scientific community, particularly with MicroTCA hardware. The framework serves as an abstraction layer that simplifies the utilization of various FPGA vendor tools, facilitates IP integration, aids in documentation creation, and offers many other benefits. In addition to FWK, DESY also provides a wealth of Board Support Packages designed for a range of MicroTCA AMC boards. This presentation will provide an overview of the FWK framework and showcase examples of open-source board support packages, demonstrating their practical utility in accelerating FPGA development for MicroTCA hardware
Our ChimeraTK software framework allows rapid C++ development of servers interfacing or extending control applications. It abstracts details of hardware access, turning them into a matter of configuration, and provides immediate integration with FWK firmware framework. Modular libraries for hardware access by commonly used busses are included in ChimeraTK DeviceAccess, which features bindings to Matlab, Python and the command line, as well a graphical user interface. ChimeraTK ApplicationCore allows multi-threaded modular design of complex servers, in code that is fully independent of used control system and hardware access. For simpler cases, readily packaged Generic Server already exists, which only needs configuration. ChimeraTK Control System Adapters allow freedom in choice of control system integration, like OPC UA, DOOCS, EPICS or Tango.
This talk gives an overview of the firmware architecture of the new controller for astronomical detectors (NGCII) developed at ESO.
The modularity of MicroTCA is reflected in the firmware design to increase re-use and allow on-the-fly configuration to match the system components.
vario-optics is manufacturer of photonic boards based on integrated planar optical waveguides. The technology has reached a high maturity level and is more and more used within several applications. It is obvious that this technology can also be used within MicroTCA based systems, providing higher bandwidth and lower power consumption besides a significantly increased robustness within harsh electro-magnetic environment.
During the presentation an introduction into the technology will be given. The advantages of the optical on-board communication will be highlighted. Later, different applications based on photonic boards and their realization will presented with special focus on high-speed on-board communication. At the end, we will give an outlook on how a Micro-TCA-based system could look like in the future.
Synchronous multi-axis motion control systems that can be integrated with diagnostic and data acquisition subsystems are integral parts of large experimental physics projects. To meet these specific requirements, DESY has developed an open-source solution based on the DAMC-MOTCTRL board. This solution is tailored for use in projects such as PETRA IV and offers the possibility to synchronously control up to 48 stepper motors with a single AMC board. Users can interact with this system through established control systems such as DOOCS, EPICS, and TANGO, or through a direct ASCII interface.
The central role of the multi-axis motion controller of driving and monitoring the stepper motors and responding to time-critical events is performed by the FPGA firmware. It is developed within the open-source framework FWK and validated using the Universal VHDL Verification Methodology (UVVM).
Building on this firmware, a C++ application, utilizing the ChimeraTK framework, takes on the task of orchestrating the motion and serving as the interface to external control systems. Leveraging ChimeraTK provides the flexibility to later on either run this application on the ARM cores within the MPSoC or externally on the AMC board via PCIe links.
This presentation will give a general overview of the hardware, firmware, and software components that make up this solution and provide information on the current status of the alpha phase for the PETRA IV beam lines.
With the upcoming upgrade of the PETRA III accelerator at DESY to PETRA IV, a renewal of most controls electronics is foreseen. For this, MTCA.4 has been chosen to become the new standard. This presentation will give a brief overview of the planned MTCA.4-based clock and timing distribution hardware for the storage ring and its pre-accelerator chain.
As main component for the timing distribution a dedicated AMC module, the DAMC-X3TIMER, is currently under development. This presentation will outline its key features and implementation on the AMC. Further on, we will present the current status of the hardware and firmware development.
The DMMC-STAMP SoM (DESY Module Management Controller System on a Module) is a comprehensive management solution for operating a target AMC in a MicroTCA based ecosystem. It comes equipped with pre-installed firmware that covers all mandatory MicroTCA management requirements, plus some useful additional features (e.g. onboard sensors, remote console and in-system-update of the MMC), making it a ready-to-use drop-in solution. Using the optional DMMC Software Development Kit (DMMC-SDK), board developers can enable additional features specific to their AMC board, such as remote console to and in-system updates of the payload FPGAs, PMBUS power management, and AMC sensor integration.
This talk gives an overview of the DMMC-STAMP and recently added features, which were motivated by development of new AMC boards at DESY and requirements of DMMC-STAMP customers. This includes configuration of multiple power management chips, serial-over-IPMB for multiple payload FPGAs, and integration of FMC sensors into IPMI monitoring.
KALDERA is a new laser plasma accelerator (LPA) built at DESY whose key element is a kHz repetition rate. This repetition rate will enable feedback control to achieve a higher level of stability and reliability than existing LPAs operating at a repetition rate of a few hertz. KALDERA, unlike the other DESY accelerators, is a CW machine, thus requirements for control and DAQ are different. In our presentation, we will show how we want to use the existing hardware and control system that was developed to control pulse accelerators to control new state-of-the-art LPA.
In recent years, FPGA vendors have integrated high-level synthesis languages (HLS) into their development tools, allowing HDL (Hardware Description Languages) to be set aside in application development.
This contribution presents the development of a Board Support Package (BSP) for the NAT-AMC-ZYNQUP-FMC board based on a Zynq UltraScale+ MPSoC that allows the implementation of data acquisition and processing applications using the HLS and OpenCL tools. The BSP hardware is divided into a static and a dynamic region. The static region provides the PCIe interface to the MicroTCA backplane and the interface with an external FMC module that features JESD204B ADCs and DACs. The JESD204B uses the open-source IPs from Analog Devices. The accelerated functions or kernels written in HLS or OpenCL are implemented in the dynamic region interface with the PCIe and JESD204B through HLS Streams. The SoC's ARM cores run an embedded Petalinux Linux distribution that handles the JESD204B configuration and provides the environment in which the kernels are executed.
Finally, a use case is presented where the BSP implements and verifies a digital pulse shape analysis algorithm of signals acquired at 1GS/s.
Thorough testing is an essential part of every design process but on the other hand takes time. Therefore, a method that allows the engineer to test a system with as little effort as possible will increase the test coverage and the quality of the final system. As Python is a general-purpose programming language that is both quick to write and easy to learn, it makes it an ideal candidate for writing test suites. Python also provides an extensive ecosystem with ready to use libraries for many use cases - for example, pytest for running tests. The low-level radio frequency (LLRF) system at the European Spallation Source is MTCA-based and consists of multiple AMCs. The integration tests of the RF-field controller FPGA firmware have been implemented with a Python test suite based on pytest. Newly developed Python modules provide access to the FPGA and the other MTCA system components, and implement functions commonly needed for testing. For example, the tests can control the local timing AMC. Such functions are either implemented on a low level or by accessing them through the control system (EPICS) where they are available. All these parts led to a test suite of several hundred tests that run on test LLRF system in the laboratory.