2nd MTCA Workshop for Industry and Research

10 Dec 2013, 13:00 → 12 Dec 2013, 19:00 Europe/Berlin

DESY Lecture Hall (DESY)

Dieter Notz (DESY), Holger Schlarb (DESY), Kay Rehlich (DESY)

The 2nd MTCA workshop for industry and research will take place from 11th to 12th December 2013 in Hamburg, Germany. DESY invites you to participate in this workshop.

The workshop will bring together experts and beginners from industry and research to discuss present and future developments in the field of MTCA. The main topics include:

• Tutorials by experts – overview on MTCA.4 (10th December, 15:00)
• Applications in research facilities
• Applications in industry
• New products
• Interoperability - further developments
• Software for MTCA.4

Supporting program

• Workshop dinner
• Tour of DESY facilities

During the industrial exhibition (11th December 2013) the newest products involving MTCA.4 modules from industry and research will be presented. You will have direct contact to the manufacturers.

Tuesday 10 December

13:00 → 15:00 Registration

14:15 → 15:00 DESY Tour 1

15:00 → 16:45 Tutorials by experts

Convener: Dr Frank Ludwig (DESY)

15:00 MTCA.4 Tutorial Basics

This tutorial covers the basics of MTCA.4. It begins with background information on why the existing MicroTCA and AMC standards did not satisfy the needs of the Physics community and what new features were required. The physical features of MTCA.4 like board sizes, connector definitions, module insertion/extraction and also the management interface between the RTM and the Front board are explained. Then it gives an overview of management features which have been added in MTCA.4 to manage the RTM and the Cooling Unit.

Speaker: Mr Dietmar Mann (Schroff GmbH)

Slides 64_Mann_MTCA.4_Tutorial_Basics_Schroff_2013.pdf

15:45 MicroTCA Management

High reliability and serviceability are two of the main requirements on xTCA systems. Furthermore a system should be flexible and versatile without raising the administration effort. Management of each single hardware component in a xTCA is therefore inevitable. The monitoring of parameters like temperatures and voltages inside the shelf, the handling of interconnections and the automatic supervision of cooling units and power modules are essential features of each xTCA system.

Speaker: Mr Christoph Stechmann (DESY)

Slides MicroTCA_Management.pdf MicroTCA_Management.pptx

16:15 MicroTCA and PCIe HotSwap under Linux

One of the main characteristics of any computer architecture is reliability and uninterrupted operation. This important if a system allows a possibility to add and remove devices in run. The Hot-Swap service is irreplaceable not only in the process of development of final devices but also in the use, thus ensuring continuous functioning of the system as a whole. Such feature plays an important role especially in control systems. In the uTCA systems the Hot-Plug is generaly provided by the Shelf Manager and the Hot_Swap services of the PCI Express Bus. One of especially important features of this bus is a possibility of hot replacement of the devices without reseting an operating system. The PCI Express Hot-Swap service is being used relatively long. However, the uTCA system makes its own amendments into general architecture of the PCIe Hot-Swap and in the methods and ways of use. For MicroTCA systems using PCIe as the base link, the Hot-Swap provided by the following various subsystems: 1. PCIe Hot-Plug controller enclosed in the PCIe root or switch ports, with the Standardized Software Interface 2. MicroTCA Shelf Manager, MMC controller 3. Hot-Swap services supplied by IPMI 4. Hot-Plug services supplied by OS (Hot-plug driver and user notification subsystems) The specificity of the MicroTCA systems is in fulfillement of certain tasks of the HotPlug Controller by the MCH and AMC. Interaction of these subsystems leads to the following three important capabilities: 1. a method of replacing of failed expansions cards without turning the system off 2. keeping the OS and other services running during the repair 3. shutting down and restarting software associated with the failed device Effective functionality of Hot-Swap system requires adjustments of all these Basic Elements. Our experience of the adjustment, starting and testing aswell as use of the PCIe Hot-Swap in uTCA architecture will be presented.

Speaker: Mr Ludwig Petrosyan (DESY)

Slides utcapciehp_s.pdf

16:45 → 17:15 Coffee Break

17:15 → 18:15 Tutorials by experts

Convener: Dr Frank Ludwig (DESY)

17:15 MTCA Tutorial: Configuring and Maintaining

The configuration and maintenance of a MTCA.4 system is presented and shown in life demos. This is a follow on tutorial to last years one "Bring up a MTCA.4 System“. (see http://webcast.desy.de/?cat=61) Covered themes are: set up PCIexpress, PCIexpress hotplug, remote firmware update (.hpm), methods to update FPGA, detection mechanism for issues, maintenance

Speaker: Mr Vollrath Dirksen (N.A.T. GmbH)

Slides MTCA_Tutorial-Configuring_and_Maintaining_(ohne_Video).pdf MTCA_Tutorial-Configuring_and_Maintaining_(ohne_Video).pptx

Wednesday 11 December

08:15 → 09:00 Registration

09:00 → 09:15 Welcome: Introduction to DESY and the European XFEL

Speaker: Dr Hans Weise (DESY)

Slides HW_mTCA_dec2013.pptx

09:15 → 09:30 Status of "MTCA.4 for Industry" Helmholtz Validation Fund

Speaker: Dr Holger Schlarb (DESY)

Slides 2nd_MTCAWS_HS_20131211_id62.pdf 2nd_MTCAWS_HS_20131211_id62.pptx

09:30 → 11:00 Applications in research facilities

Convener: Mr Matthias Balzer (KIT)

09:30 Discussion of Future MicroTCA.4 Standards Extensions and Brief Overview of SLAC Programs

The MicroTCA.4 development under the PCI Industrial Computer Manufacturers Group (PICMG) is proving successful in meeting a large range of needs for accelerator controls and instrumentation. A number of further extensions have been undertaken by DESY for the XFEL program for RF distribution which raises the question of preserving interoperability within the standard as important new solutions are discovered. Similarly the Zone 3 connector space has been specified functionally for a class of fast ADC-DAC use cases, in particular Low level RF and Beam Position Monitors, which suggests standards definition formalization wider than the current use cases. Common reference designs for AMC and RTMs are another area of need. In the software-firmware space, now bolstered by real experience, labs and industry can begin to converge on preferred architectures and software-firmware interface standards or at least guidelines for Best Practices. Prior work done in this area by the Software Working Group, reported separately, needs to be resumed and level of effort expanded. The SLAC overview will refer to recent accomplishments as well as planning in progress for the 2-mile accelerator CAMAC control system upgrade. The presentation covers the work of many contributors. The xTCA for Physics leading committee members for Hardware Working Group were Robert Downing, Dick Somes, Vince Pavlicek, Kay Rehlich, Tomasz Jezynski, Dietmar Mann, Michael Thompson, Eike Waltz , Jean-Pierre Cachemiche and others. Key Software Working Group leaders were Stefan Simrock, Gus Lowell, Zhen’An Liu, Dariusz Makowski, Jorge Sousa, Michael Thompson and others. The SLAC MTCA.4 development team members are Andrew Young, Charlie Xu, Sonya Hoobler, Till Straumann, Ernest Williams, Kukhee Kim, Bo Hong, Thuy Vu, David G. Anderson, Dan van Winkle, Debbie Rogind, Tom Himel and others. Zheqiao Geng, a major contributor, has recently joined PSI in Switzerland.

Speaker: Raymond Larsen (SLAC National Accelerator Lab)

Slides DESY_2nd_MTCA_4_Workshop_Dec_11-12_2013_R10-RLarsen.pdf

09:45 Update on MTCA.4 for FLASH and XFEL

MicroTCA will be used for all fast data acquisition systems of the European-XFEL. First MicroTCA installations for this project are currently commissioned. After a longer shut-down FLASH was equipped with several MicroTCA systems as well. These systems are used successfully in the daily operations. Further MicroTCA crates for a second undulatory beam line are being installed these days. The status of and experience with various MicroTCA components of these projects will be given.

Speaker: Kay Rehlich (DESY)

Slides MicroTCAatDESY.pptx

10:00 Evaluation results of MicroTCA equipment at CERN

MicroTCA is a candidate platform for modular electronics for the upgrade of the current generation of high energy physics experiments at CERN. Driven by the rising interest in this standard, the Electronic Systems for Experiments group has launched in 2011 an evaluation project with the aim of performing technical evaluations and eventually providing support for equipment procured on a large scale by LHC experiments. Different devices from different vendors have been acquired, evaluated and interoperability tests have been performed. This presentation shows the test procedures and facilities that have been developed for this purpose and focuses on the evaluation results including electrical, thermal and interoperability aspects.

Speaker: Mr Matteo Di Cosmo (CERN)

Slides M_DICOSMO_Evaluation_results_MicroTCA_at_CERN.pptx

10:15 Diagnostic Use Case Examples in different form factors (MTCA.4, ATCA, PXIe)

ITER requires extensive diagnostics to meet the requirements for machine operation, protection, plasma control and physics studies. Most of the extremely complex ITER diagnostics systems are provided by the ITER Domestic Agencies (DAs) and their partners. On their demand the IO has created several diagnostics use case examples in different form factors (MTCA.4, ATCA, PXIe) to enhance the understanding of diagnostics Plant System I&C and the associated deliverables. The use cases come complete with documentation and implementation, further helping the DAs, their suppliers and diagnostic responsible officers to meet the ITER diagnostics requirements. In this paper, we present the current status and achievements in implementation and documentation with focus on the MTCA.4 form factor.

Speaker: Dr Stefan Simrock (ITER)

Slides Diagnostics_UC_long.pdf Diagnostics_UC_short.pdf

10:30 Experience with the MTCA.4 LLRF System at FLASH

The Free Electron Laser in Hamburg (FLASH) provides ultra-short laser pulses down to a wavelength of 4.2 nm. Precision regulation of the RF fields is done by a fast digital LLRF system which has been recently upgraded to the MTCA.4 based platform. Installations inside the acceleration tunnel require a stable and reliable system due to a radiated environment and limited access. Installation routines and platform related issues have been investigated to gain experience for the next larger scale installation at the European XFEL. For the first time it has been shown that the MTCA.4 based LLRF system is capable to run at a user facility for permanent operation with outstanding performance.

Speaker: Mr Christian Schmidt (DESY)

Slides MTCA_Workshop_2013.pptx MTCA_Workshop_2013_Schmidt.pdf

10:45 MTCA.4-based LLRF system tests at ELBE

ELBE (Electron Linac for beams with high Brilliance and low Emittance) is a multi-purpose radiation source at HZDR (Helmholtz-Zentrum Dresden-Rossendorf). LLRF system controls two normal conducting buncher cavities (one operating at 260 MHz and one at 1300 GHz), a super-conducting gun cavity and 4 super conducting TESLA-type accelerating cavities. The existing analog feedback loop satisfies field stability requirements, but lacks flexibility of a digital system. At the beginning of November a MTCA.4-based single cavity regulation system performance was evaluated. This paper describes system’s architecture, discusses achieved results and possible future system developments.

Speaker: Mr Michael Kuntzsch (HZDR)

Slides MTCA_Workshop_2013_Kuntzsch_talk.pdf

11:00 → 11:30 Coffee Break

11:30 → 13:10 New products

Convener: Mr Tobias Hoffmann (Helmholtzzentrum für Schwerionenforschung GSI GmbH)

11:30 Improving Functional Density

Industry expects the capabilities and performance density of systems to improve over time. This presentation will look at how new chassis and infrastructure elements maximise the space available for payload, packing more capability into smaller spaces.

Speaker: Balasubramanya Bellur Hiriyannaiah (Vadatech Ltd)

Slides DESY_VadaTech_-_Improving_Functional_Density.pptx

11:40 Upgrade to 16 PCIexpress lanes in MTCA.4

This presentation shows a solution to overcome the bottleneck in the data path of the main CPU (root complex), if all IO boards transfer their data via 4 lane PCIexpress DMA. By default all AMC slots offer 4 lanes of PCIexpress transfers. By extending the data path to the local CPU of the NAT-MCH-PHYS64 no modification in the backplane of the MTCA.4 crates is needed to offer a 16 lane PCIexpress path to the main processing CPU.

Speaker: Mr Vollrath Dirksen (N.A.T. GmbH)

Slides Upgrade_to_16_PCIe_lanes_in_MTCA.4.pdf Upgrade_to_16_PCIe_lanes_in_MTCA.4.pptx

11:50 Kontron product strategy

The philosophy of designing MTCA products

Speaker: Andreas Geisler (Kontron)

Slides Kontron_Desy_MTCA_Workshop_2013.pptx

12:00 Pentair / Schroff MTCA.4 products

Pentair/Schroff is one of the companies actively contributing in the development of the PICMG MTCA.4 Standard. Since the last MTCA.4 workshop at DESY in December 2012, Pentair/Schroff has upgraded its MTCA.4 product portfolio. The presentation shows the range of Schroff products which comply with MTCA.4: - 12 Slot MTCA.4 chassis with redundant Cooling Units in a push-pull configuration. - 12 Slot MTCA.4 for LLRF applications. - 7-Slot MTCA.4 chassis for laboratory use. - 5-Slot MTCA.4 chassis with 2U chassis height and horizontal AMC Module mounting. - MTCA.4 accessories: Filler / Blocker /Slot Separation Modules.

Speaker: Mr Dietmar Mann (Schroff GmbH)

Slides 25_Mann_MTCA.4_Product_Presentation_Schroff_2013.pdf

12:10 MTCA.4 hardware solutions

This talk will show hardware solutions for different demands in field ELMA as a hard ware provider will show scalable products from 1U to 9U Different accesories will round up this presentaion

Speaker: Mr Aksel Saltuklar (ELMA)

Slides MTCA_1410_1411_DESY.pdf

12:20 The SIS83xx MTCA.4 Digitizer AMC family and associated RTMs

Struck is an early adopter of the MTCA.4 Standard. The well known 125 MSPS 16-bit SIS8300 V2 and SIS8300-L Xilinx Virtex 5 and 6 based cards will be complemented by the 250 MSPS 16-bit SIS8325 shortly. In parallel DESY's 10 channel DWC10 downconverter and the 8 channel downconverter one channel vector modulator DWC8VM1 RTMs are license products for LLRF applications.

Speaker: Dr Kirsch Matthias (Struck Innovative Systeme GmbH)

Slides 68-Kirsch-Struck-091213.pdf

12:30 MTCA.4 Front End Processing

The best that the technology can provide in MTCA.4 Signal Processing

Speaker: Mr Thierry Wastiaux (Interface Concept)

Slides IC-Thierry_MTCA.4_Workshop_V2_2013-12.pdf

12:40 1000W Low Noise MTCA.4 Power Supply

The high power and low noise MTCA.4 power supply made by WIENER Plein & Baus GmbH in Germany features 1000W of total DC output power and further reduced noise & ripple figures. The latest version of this unit includes improved functions for setup and maintenance.

Speaker: Mr Thomas Berner (WIENER Plein + Baus GmbH)

Slides MTCA.4_WS_2013_WIENER.ppt

12:50 PRESENTATION OF HIGH-VOLTAGE MODULES IN MTCA.4 STANDARD at CAENels

Presentation of a new multi-channel High-Voltage power supply module in AMC.0 rev2 format for MTCA.4 rev1 or MTCA.0 rev1 systems.

Speaker: Mr Simone Farina (CAEN ELS d.o.o.)

Slides CAENels_-_MTCA_Workshop_-_11122013.ppt

13:00 New MTCA.4 products from IOxOS Technologies SA

IOxOS Technologies SA introduces a new MTCA.4 product line based on its most powerful VME64x platform, the IFC_1210 FMC/XMC Intelligent FPGA Controller, and a comprehensive family of ADC mezzanines in FMC form factor, already deployed on particle accelerator control systems in some of the most reputed institutes of Physics. The new MTCA.4 product line features VITA 57.1 FMC High Pin Count (HPC) carriers powered by Virtex-6T FPGA devices and optimized development kits, ensuring total compatibility with its successful and widely deployed VME64x counterpart. The following two boards are the cornerstone of the new MTCA.4 product line: (1)The MTCA.4 IFC_1410, a Single Board Computer which leverages a Freescale QorIQ P2020 running Linux with RT extension or VxWorks, combined with a Xilinx Virtex-6T FPGA connected to a local PCIe GEN2 infrastructure. A PCIe GEN2 Switch -with configurable port operation modes (UPstream, DOWNstream, Non-transparent, Partition) manages the interconnection of on-board PCIe resources and peripherals, together with the attachment to the two AMC PCIe ports. The Virtex-6T FPGA, connected to the local PCIe infra-structure, controls one VITA 57.1 FMC slot. All MTCA.4 specific features are fully integrated on-board. An XMC mezzanine can be optionally plugged instead of the FMC, enhancing the interconnect capability of the solution (2)The MTCA.4 RTM_1411, a dual VITA 57.1 FMC carrier featuring a Xilinx Virtex-6T FPGA -connected to the local PCIe infrastructure through the RTM connector- to control both FMC HPC slots To overcome the challenge of the Virtex-6T FPGA programming, the IFC_1410 and the RTM_1411 are delivered with the TOSCA II FPGA Design Kit solution, a comprehensive FPGA design environment which provides full visibility and facilitates the integration of the user application within a PCIe GEN2 switch centric architecture. This approach makes possible the implementation of a complete Network on Chip (NoC) solution which includes PCIe EP, four dedicated DDR3 Memory Controllers with built-in DMA capabilities and programmable QoS for local data buffering (enabling a sustained bandwidth of 4 x 1.6 GBytes/s), and fully customizable embedded user areas tightly coupled with these resources. TOSCA II also includes reference designs, Bus Functional Models (BFM) for simulation purposes and full access to VHDL source code. The MTCA.4 product line is enhanced with the ADC_311x series, a comprehensive family of ADC mezzanines in FMC form factor providing high-performance data acquisition capabilities including: - ADC_3110: Eight channels ADC 16-bit 250 Msps, AC/DC coupled - ADC_3111: Dual channels DAC 16-bit 500 Msps and Dual channels ADC 16-bit 250 Msps - ADC_3112: Quad channels ADC 12-bit 1 Gsps, DC differential coupled

Speaker: Mr Joel Bovier (IOxOS Technologies SA)

Slides MTCA_1410_1411_DESY.pdf

13:10 → 13:30 Group Photo

13:30 → 14:15 DESY Tour 2

13:30 → 14:30 Lunch

14:30 → 15:50 New products

Convener: Mr Markus Joos (CERN)

14:30 Beyond 10 Gbps with MTCA.4

Digital systems used in high speed telecommunication applications, complex data acquisition or control systems of modern Physics transmit enormous amount of data. Every day people break the limits introducing new hardware, standards and protocols allowing transmission of data with higher throughput. The MTCA.4 hardware was successfully verified with protocols sending data via a single channel with throughput up to 6.25 Gbps. However, there is still open questions if the standard is ready for protocols beyond 10 Gbps. In this talk we will present a Kintex 7-based, high-speed data processing module, developed within HVF-0016, capable of sending data with total throughput above 280 Gbps. The first results of data transmission measurement for various MTCA.4 backplanes will be presented.

Speaker: Dr Dariusz Makowski (Lodz University of Technology, DMCS)

Slides D.Makowski_Beyond_10G_with_MTCA.4_v3.pdf

14:40 High speed interface simulation using the new 3D layout HFSS interface

A new 3D Layout interface and meshing technology for the industry standard high frequency structure simulator is shown on example of a PCIe interface, enabling fast and parameterized simulation of physical layer structures as well as their optimization. Statistical methods for data eye calculation and the usage of IBIS AMI and spice models are shown, as well as coupling to thermal and computational fluid dynamics simulations.

Speaker: Mr Simon Muff (Ansys Germany GmbH)

Slides High_speed_interface_simulation_using_the_new_3D_layout_HFSS_interface.pdf

14:50 New 32 Channel ADC design

This talk describes an MTCA.4 compliant AMC and µRTM for high channel count analog to digital conversion applications, developed within HVF. The AMC provides 32 ADCs with 12 or 14 Bit resolution. Depending on the ADC used, sample rates up to 20 Msps are possible. A powerful clock distribution allows the use of backplane-distributed or on-board generated clocks as ADC sample clock. A Kintex-7 FPGA provides the ability to transfer ADC data via x4 PCI-Express Gen 2. In addition, on-board DDR3 memory allows to store ADC data for subsequent readout. The ADCs analog inputs connect to a µRTM via Zone 3 with a pin assignment according to Class A1.2. Signal conditioning and analog input connectors are located on the µRTM, allowing easy adaption to different user requirements.

Speaker: Mr Niels Koll (TEWS Technologies)

Slides This talk describes an MTCA.4 compliant AMC and µRTM for high channel count analog to digital conversion applications, developed within HVF.

15:00 MTCA.4 RF-Backplane Option : Features and Management

Recently developed RF Backplane (uRFB) option for MTCA.4 crates allows for significant extension of crate capabilities. The backplane was developed to distribute low noise RF signals and high-precision, low-jitter clock signals to RTM cards. The hot-swap feature for RF signals allows the MTCA.4 crate users to build system with multi-channel analog signal processing without many coaxial RF cables connected to front panels of RTM cards. This improves system management, allows for cost reduction and simplifies system maintenance. The uRFB also offers possibility to supply RTM cards with managed, bipolar, high-performance (analog) power from two rear power modules independent from the noisy, digital AMC ones. Finally, uRFB concept defines extended RTM (eRTM) cards in the volume behind front power supplies and MCH cards not used by the standard MTCA.4 crate. Developed eRTM cards offer additional space that can be used for applications requiring more space than is available on uRTM cards. This contribution describes the RF Backplane concept, management idea and performance measurement results.

Speaker: Dr Krzysztof Czuba (Warsaw University of Technology)

Slides 2013_12_11_uRFB_MTCA_Worksh_Czuba.pdf

15:10 High speed AMC Digitizer and RTM based application modules

This contribution describes the design of an Advanced Mezzanine Card (AMC) in the MTCA.4 standard suited for direct analog-to-digital conversion of high-frequency signals up to 2.7 GHz with a maximum ADC clock frequency of 800 MHz. Signal conversion is performed using the undersampling technique. This card was designed for the needs of the LLRF and other control and measurement systems of the FLASH and XFEL accelerators. The AMC is compliant with the A1.1 Analog class for MTCA.4 AMCs. The designed module consists of eight very-high-speed ADC channels, four high-speed and precision DAC channels, a powerful FPGA unit, fast SRAM memory, along with special power supply and diagnostic circuits. The AMC digitizer work in pair with various project-specific Rear Transition Modules (RTMs). This paper describes details and parameters of the digitizer AMC and the specialized RTMs, as well as performance and usage of direct sampling of high frequency signals.

Speaker: Maciek Grzegrzółka (ISE/WUT)

Slides sbouhab_mtca_2013.pdf

15:20 High-Speed AMC to PC bridge

The AMC Bridge (AB) is a small form factor multipurpose interface board targeted to users of Advanced Mezzanine Cards (AMCs) that has been designed at CERN by PH/ESE group. Its intended use is to enhance the stand-alone capabilities of the AMCs by exploiting some features only accessible through the AMC connector thus forming a compact bench-top system ideal for development and test purposes. Besides delivering power to the hosted AMC, the AB provides external access to two differential input/output clock lines and ten high-speed serial lanes divided in three groups: two lanes featuring respective Small Form-factor Pluggable Plus (SFP+) sockets, four lanes sharing one Quad Small Form-factor Pluggable Plus (QSFP+) socket and four PCIe Gen2 (Gen3 upgradable) dedicated lanes sharing one iPass socket.

Speaker: Mr Manoel Barros Marin (CERN)

Slides M_Barros_Marin_2nd_MTCA_workshop_DESY_2013.pdf

15:30 Middleware Technologies: The Software Bridge into the Industry

MTCA.4 is an interesting technological approach that is well suited to usage in sophisticated control systems for automation, medical technology and testing. However, for this approach to be successful users need access to appropriate software technologies.

Speaker: Mr Robert Schachner (RST Industrie Automation.GmbH)

Slides SchachnerMTCA4.pptx

15:40 From MicroTCA to ATCA. Scalability issues for data acquisition systems.

During hardware work on data acquisition systems, eicSys has evaluated several form factors and mezzanine standards. First of the most important requirements defined by customers is a system scalability from several analog channels up to thousands. Second one, very important for some customers, is reliability; therefore, ATCA and uTCA standards has been selected for further development. The decision has been made to use a carrier-mezzanine approach, since it provides great flexibility in terms of board compatibility, upgrade costs and software compatibility. After investigations a custom mezzanine board and its interface has been defined and two types of carrier boards have been designed: ATCA blade and MTCA.4. The mezzanines are custom driven boards with different requirements such as number of channels, sampling frequency for ADCs, special filtering of input signals and so on. The ADC mezzanine with 24 channels and special filtering features has been designed for detectors readout. Another types of ADC mezzanine boards with 20 and 40 channels (different precision and ADC sampling frequency) have been designed for a control and diagnostic system required by fusion energy experiments. A modular approach together with the development of 1U MTCA.4 chassis and enhanced for a high precision instrumentation ATCA backplane gives possibility to build scalable systems from a few analog channels (1U chassis) up to several hundreds analog channels (ATCA 14-slot crates) using the same type of mezzanine module. Different platform (ATCA and MTCA.4) offers diversified processing power and reliability level. Functionality of MTCA.4 based system might be extended with DAMC-FMC20 MTCA.4 carrier and any available on the market FMC board. It gives a wide range of possibilities for system design.

Speaker: Mr Friedrich Fix (Eicsys Embedded Integrated Control Systems)

Slides Eicsysws13.pdf Eicsysws13.pptx

15:50 → 16:00 Discussion, Birds-of-Feather (BoF) interest groups

Vollrath Dirksen(N.A.T. GmbH)

16:00 → 20:00 Exhibition

20:00 → 22:00 Dinner

20:00 → 22:00 Exhibition

Thursday 12 December

09:00 → 10:45 Applications in research facilities

Convener: Mr Vollrath Dirksen (N.A.T. GmbH)

09:00 XFEL Machine Protection System (MPS) Based on MicroTCA

The European X-Ray Free Electron Laser (XFEL) linear accelerator will provide an electron beam with energies of up to 17.5 GeV and will use it to generate extremely brilliant pulses of spatially coherent xrays. With a designated average beam power of up to 600 kW and beam spot sizes down to few micrometers, the machine will hold a serious damage potential. To ensure safe operation of the accelerator it is necessary to detect dangerous situations by closely monitoring beam losses and the status of critical components. This is the task of the MicroTCA based machine protection system (MPS). Many design features of the system have been influenced by experience from existing facilities, particularly the Free Electron Laser in Hamburg (FLASH), which is a kind of 1:10 prototype for the XFEL. A high flexibility of the MPS is essential to guarantee a minimum downtime of the accelerator. The MPS is embedded in the DOOCS* control system. DOOCS: Distributed Object Oriented Control System

Speaker: Mr Sven Karstensen (DESY)

Slides Karstensen_MTCA_workshop_.pptx

09:15 A general MTCA.4-based laser to RF synchronization system

The first MTCA.4 based laser synchronization system is presented. We use a standard MTCA.4 crate where a high frequency RF front-end detector feeds a fast digitizer AMC board. The processing is carried out in the FPGA located on the digitizer which transmits the control output over a serial link routed on the standard AMC backplane to a receiver FPGA located on a neighboring AMC board. The hosting FPGA on this board transmits the control signal to the DACs on the RTM side which is composed of high voltage piezo pre-amplifiers and high-voltage piezo drivers. The piezo driver acts on the piezo stretcher of the Er-fibre laser which controls the frequency of the laser resonator. Such solution opens many possibilities for processing algorithms and connectivity with other system. Some of the main limitations and their mitigations are presented.

Speaker: Uros Mavric (DESY)

Slides MTCA_4_WS_Laser_Synch_Mavric.pdf MTCA_4_WS_Laser_Synch_Mavric.pptx

09:30 MicroTCA @ CMS

The CMS experiment at the LHC at CERN has decided to upgrade their readout hardware at a large scale from VME to MicroTCA . In this talk major parts of the upgrade will be introduced. As a typical use case in the HEP environment the migration from VME to MTCA.0 will be discussed for a readout crate of a sub detector. The AMC boards developed by the collaboration will be introduced with a focus on the AMC13 board. This board is placed in the second MCH slot and exploits the connectivity in this slot and is the central part of all the main CMS MicroTCA upgrade projects.

Speaker: Ulf Behrens (DESY)

Slides uTCA_@_CMS_(MTCA_workshop_2013)-2.pptx

09:45 Intra-pulse RF feedbacks for normal conducting cavities with femto-second precision

In this contribution, we will present first results of single cavity RF control based on MTCA.4 at REGAE. With the new system design we reduce the system latency down to 600ns, with still room for improvement. This new latency reduced design, allows us to implement an intra-pulse RF feedback for the normal cunducting RF Gun at REGAE. The inloop RMS pulse to pulse jitter were reduced below 30fs.

Speaker: Dr Matthias Hoffmann (DESY)

Slides 22_MHoffmann.pdf

10:00 Open hardware / open software MTCA.4-based beam position measurement system

The Brazilian Synchrotron Light Laboratory (LNLS) is developing a BPM and orbit feedback system for Sirius, the new low emmitance synchrotron light source under construction in Brazil. In that context, 5 open-source boards and accompanying low-level firmware / software were developed in cooperation with the Warsaw University of Technology (WUT) and Creotech Instruments SA to serve as hardware platform for the BPM data acquisition and digital signal processing platform as well as orbit feedback data distributor. The experience of integrating the system prototype in a COTS MicroTCA.4 crate will be reported as well as the planned developments.

Speaker: Mr Grzegorz Kasprowicz (Warsaw University of Technology / Creotech Instruments SA)

Slides MTCA_workshop_G.Kasprowicz.pdf

10:15 MicroTCA for the Optical Synchronization Systems at XFEL and FLASH

The optical synchronization system which is responsible for providing a femtosecond stable timing reference for beam diagnostics, laser synchronization, and the LLRF control at Flash and the European XFEL will use MicroTCA hardware for signal detection, feedback control, and actuator driving. For these purposes some special and some general purpose modules (AMC, RTM, FMC) have been developed. This talk gives a brief introduction to the system and the planned topology of the MicroTCA hardware.

Speaker: Mr Matthias Felber (DESY)

Slides 13'12_Felber_MTCA-WS.pdf

10:30 ATCA/MicroTCA based Compute Nodes in the Belle II Pixel Detector DAQ

In this talk we present the application of the MicroTCA based Compute Node in the Belle II experiment at KEK, Japan. The system comprise an ATCA carrier board and AMC board design based on Virtex-4 FX60 and Virtex-5 FX70T FPGAs. It is designed to perform data acquisition of 22 GB/s and data reduction by a factor <10 at the Belle II pixel detector. The firmware programming comprises buffer management with pointer lookup tables, DDR2 memory access using NPI (native port interface), optical link data transfer using GTX transceivers and Aurora 8B/10B, SERDES links and custom UDP and TCP/IP interfaces. A parallel region-of-interest (ROI) algorithm performs data reduction of the PXD data based upon charged track extrapolation from the high level trigger and silicon strip vertex detector, arriving with a large latency and out of order. First test of the full DAQ readout chain with a scaled down system, using a uTCA shelf instead of the carrier boards, have been performed recently at DESY as preparation for a beam test in January 2014.

Speaker: Dr Bjoern Spruck (University Giessen)

Slides spruck_desy.pdf

10:45 → 11:15 Coffee Break

11:15 → 12:25 Applications in research facilities

Convener: Raymond Larsen (SLAC)

11:15 Femtosecond bunch arrival time monitoring with precision FMC-ADC modules

Bunch Arrival time Monitor (BAM) is an electro-optical device used at FLASH accelerator in DESY for the high precision, femtosecond scale, measurements of the moment when electron bunch arrives at the reference point in the machine. The arrival time is proportional to the average bunch energy, and is used to calculate the amplitude correction for RF field control. New MTCA.4 devices, dual FMC carrier and specialized ADC FMC module, has been used to upgrade VME based BAM readout electronics. In this talk new MTCA devices and the first measurement results will be presented and compared with old VME system.

Speaker: Mr Jaroslaw Szewinski (NCBJ)

Slides jszewins_mtcaws2013.pdf

11:29 Control and Data Acquisition of the Wendelstein 7-X Experiment

Wendelstein 7-X is a nuclear fusion experiment based on magnetically confined plasmas. Since nuclear fusion has the potential to be a long term primary energy source, Wendelstein 7-X investigates the reactor capabilities of an advanced stellarator. In contrast to its predecessor, Wendelstein 7-X is equipped with superconducting magnets for enabling steady state plasma operation and access to data acquisition system is quite often restricted. Therefore, the remote monitoring and configuration features and the compactness of MTCA based data acquistion systems are of great advantage for the experiment operation.

Speaker: Dr Andreas Werner (MPI f. Plasmaphysik)

Slides werner-MTCAII.ppsx

11:43 Image Acquisition and Processing with MTCA.4

A wide variety of methods employed in diagnostic systems of large-scale physics experiments is based on data from visible and infrared light cameras. Observation of rapid physical processes requires the application of high-speed cameras, therefore the imaging systems should support high-performance image acquisition and processing. The systems should be also easily scalable and should allow the synchronization of a few cameras with each other and with other sensors. The presentation will show MTCA-based system dedicated for data acquisition from ultrafast high-resolution cameras with Camera Link interface. The system supports data transfer with throughput up to 6.3 Gbit/s for single camera. Thanks to the modular structure of MTCA.4 architecture the system is scalable and can handle multiple cameras. The ability of connecting multiple cameras to single MTCA chassis greatly facilitates their synchronization as well as data acquisition and processing. Software developed for the system ensures primarily data acquisition and cameras control and monitoring. Moreover, it allows images recording and offline analysis. It also implements a set of basic algorithms for image processing.

Speaker: Piotr Perek (Lodz University of Technology, Department of Microelectronics and Computer Science)

Slides Image Acquisition and Processing with MTCA.4 - Presentation

11:57 Design of a Stripline BPM System on MicroTCA.4

SLAC National Accelerator Laboratory is a premier photon science laboratory. SLAC has a Free Electron Laser facility that will produce 0.5 to 77 Angstroms x-rays and a synchrotron light source facility. In order to achieve this high level of performance, the beam position measurement system needs to be accurate so the electron beam bunch can be stable. We have designed a general purpose stripline Beam Position Monitor (BPM) system that has a dynamic range of 10pC to 1nC bunch charge. The BPM system uses the MicroTCA (Micro Telecommunication Computing Architecture) for physics platform that consists of a 16-bit ADC module (SIS8300 from Struck) that uses the Zone 3 A1.x classification for the Rear Transition Module (RTM). This paper will discuss the RTM design, architecture, and performance measurements of this system using the SLAC LINAC. The RTM architecture includes a bandpass filter at 300MHz with 15 MHz bandwidth, and an automated BPM calibration process. The RTM communicates with the AMC FPGA using a QSPI interface over the zone 3 connection. The system is also going to be used at the Pohang Accelerator Laboratory with the newly designed xFEL facility. Work supported by U.S. Department of Energy under Contract Numbers DE-AC02-06CH11357, DE-AC02-76SF00515, and WFOA13-197

Speakers: Andrew Young (SLAC), Chengcheng Xu (SLAC)

Slides Stripline_BPM_mtcaws.pdf Stripline_BPM_mtcaws.pptx

12:11 Low-latency 1D image detector realized as an AMC module

XFEL and FLASH machines use magnetic chicanes for compressing the electron bunches and hence obtaining higher beam peak current. To monitor the operation of the bunch compressors the spatial charge profile should be evaluated. As the bunch is traveling through the beam pipe with relativistic speed it is a very hard task to measure its parameters. One of the methods to do so is by setting an electro-optic crystal near the beam trajectory and analysing femtosecond laser pulses passing thorough the crystal. The presentation will cover design, debugging and evaluation of low-latency 1D image acquisition system realized in the MicroTCA. The talk will provide information on the experimental setup, dedicated readout circuits, die to PCB bonding and other interesting design challenges.

Speaker: Mr Aleksander Mielczarek (Lodz University of Technology)

Slides mielczarek_irs.pdf mielczarek_irs.pptx

12:25 → 12:30 Short Break

12:30 → 13:30 Applications in industry

Convener: Mr Dietmar Mann (Schroff GmbH)

12:30 Novel Applications of MicroTCA

MicroTCA is a powerful architecture that provides benefits over competing solutions in size, price/performance and platform robustness, but is often overlooked when it is viewed as a cut-down version of AdvancedTCA. This paper looks at some specific applications where MicroTCA has been applied, across market segments, to solve particular customer problems.

Speaker: Mr Ian Shearer (VadaTech Ltd)

Slides DESY_VadaTech_-_Novel_Applications_of_MicroTCA.pptx

12:45 MicroTCA application in the industry

From the idea to the real product; how to implement MicroTCA in the printing industry. This talk contains how the VME based old hardware was changed to the new MicroTCA based philosophy. From the thermal challenges to the performance challenges of the CPUs, a long way through the engineering will be shown in this presentation.

Speakers: Mr Aksel Saltuklar (ELMA), Mr Andreas Geisler (Kontron)

13:00 MicroTCA based universal Satellite Testbed

The presentation will explain a real existing user application. It will describe the applicationenvironment, as well as the reason for the customer decision. In the presentation the pros and cons of the existing solution will be explained and compared against the new system. It will showcase also some aspects with regards to system integration and possible pitfalls due to backplane topology.

Speaker: Mr Thomas Holzapfel (powerBridge Computer)

Slides pBC_2013-10-30_pBC_Industrial_solution_RUAG.ppt

13:15 4-channel Piezo Driver RTM for Lasers, Fiber Links and LLRF Cavity Tuners

The Digital Rear Transition Module 4-channel Piezo Driver (DRTM-PZT4) is in charge of driving/sensing piezoelectric based actuators/sensors used in the accelerator instrumentation applications, especially to control: synchronization of pulsed lasers, fiber link stabilization and LLRF cavity tuner. The module is complaint to the MTCA.4 standard. The RTM provides high voltage, high current output signals. The Piezo driver accepts low voltage input signals (on-board DAC or external source) which are low-pass filtered and amplified by power amplifiers to drive active piezo elements. The feedback information from piezo sensors is initially conditioned using precision amplifiers, digitized using ADC and sent back to the digital controller (AMC module). The DRTM-PZT4 provides several diagnostic signal readings: DAC output voltages, power amplifier input and output voltages and currents, high voltage power supply and temperature sensors. The on-board switches allows several configurations such power amplifier input source selection and conditioning, programming the analog active filters, changing the actuator/sensor functionality, as well as selecting the input/output voltages range of the DAC/ADC circuits. The power amplifiers can be supplied using internal or external power supply. The RTM is closed inside metal housing to improve EMI and to prevent user protection of touching the high voltages.

Speaker: Dr Konrad Przygoda (TUL/DESY)

Slides MTCA.4_2_abstract_67.pdf

13:30 → 14:15 DESY Tour 3

13:30 → 14:30 Lunch

14:30 → 15:45 Interoperability - further developments

Convener: Dr Andreas Werner (MPI f. Plasmaphysik)

14:30 Preliminary Functional Tests of the DRTM-LOG1300 Assembly

The DRTM-LOG1300 (uLOG) is a MTCA.4 compliant multi-channel local oscillator generator and high frequency signal and clock fan-out module. The module provides the fanout for 9 high frequency reference, 9 local oscillator and 9 calibration signals in the range from 400MHz to 6GHz. In addition, the module provides 22 configurable low jitter differential clock signals in the range up to 160MHz for high-precision ADC sampling applications. The uLOG assembly consists of two boards, the uLOG-RF that generates the CAL, and LO signals from the input REF, and the uLOG-Carrier that distributes these signals, as well as a Clock to the custom RF back-plane. Both boards have been manufactured and tested, as an assembly, for noise and RF characteristics. This data, as well as the final mechanical design, is presented.

Speaker: Mr Tony Rohlev (TSR Engineering)

14:45 MMC V1.0 - DESY Starter Kit for MTCA.4 Module Management

The talk will present the MMC V1.0 software framework for management of MCTA.4 cards. This framework is a "drop-in" module that can be used to implement management of MTCA.4 cards in a very short time. To allow fast development, DESY also created a hardware reference Platform "MMC V1.0 Starter Kit" that will be presented in the talk. The kit contains an example design for an AMC and a RTM board and can be used without modifications in custom hardware due to availability of source code and schematics.

Speaker: Mr Michael Fenner (DESY)

Slides mtcaws_mmc_presentation_final.pdf mtcaws_mmc_presentation_final.pptx

15:00 EMI test board

The AMC-EMI test board is an AMC board aimed to investige and qualifiy the EMI perturbances (conductive coupling mode) in MTCA system. The board allows for: measurement of power supply voltages at AMC connector (3.3V_MP, 12V_PP), measurement of low voltage drops caused by currents flowing through ground planes of PCBs or through the crate, introduction of distortion to the AMC-EMI board or other boards in MTCA crate, measurement of influence of the introduced distortions to measurement errors depending on the location and coupling mode of sensing amplifiers, measurement of influence of the introduced distortions to neighbouring boards and also measurement of vibrations of the AMC board. The presentation explains the functions of the board and shows possible measurement scenarios.

Speaker: Dr Tomasz Owczarek (ISE PW)

Slides AMC-EMI_MTCA_workshop2013_DESY.pdf

15:15 EMI compliant design of MTCA.4 modules

The MTCA.4 architecture is specially designed to fulfil the demands of scientific instrumentation with of-the-shelf modules. The use of MTCA.4 in accelerator control is exemplary for applications where there is a mix of highly sensitive analog signals and fast switching digital data. Minimizing the noisefloor results in restrictions for the EMI design of the board. The direct coupling of signals and - even more important - the coupling via the power/ground system of the board must be avoided. The complexity of the board design makes it difficult to directly control the coupling paths. The only way to an EMI compliant design is the use of design rules comprising layer stack-up, routing of signals and decoupling of components. Special attention has to be paid to the layout of the reference planes

Speaker: Dr Heinz-Hartmut Ibowski (brightONE ES GmbH)

Slides EMI_compliant_design_of_MTCA.4_modules_-_Ibowski.pdf

15:30 Ratified ZONE 3 classes to achieve enhanced AMC-RTM modularity

To enhance the compatibility and modularity of AMC and RTM boards, more and more board manufacturers follow the ratified ZOME3 classes for analog or digital applications. Here, we present the zone description, electrical specifcation, protection sequence and give design examples for application engineers. Future classses will be discussed.

Speaker: Dr Frank Ludwig (DESY)

Slides MTCA_Workshop_12_12_13_Zone_3_FLudwig_V1_final.pdf MTCA_Workshop_12_12_13_Zone_3_FLudwig_V1_final.ppt

15:45 → 16:15 Coffee Break

16:15 → 17:45 Software for MTCA.4

Convener: Mr Uwe Tews (TEWS Technologies GmbH)

16:15 Driver and Software for MTCA.4

The DESY MTCA.4 User tool kit (MTCA4U) provides drivers, and a C++ API for accessing the MTCA devices and interfacing to the control system. The PICe driver is universal for basic access to all devices developed at DESY. Modularity and extendability allow to generate device-specific drivers with a minimum of code, inheriting the functionality of the base driver. A C++ API allows convenient access to all device registers by name, using mapping information which is automatically generated when building the firmware. A graphical user interface allows direct read and write to the device, including plotting functionality for recorded raw data. Higher level applications will provide callback functions for easy integration into control systems, while keeping the application code independent from the actual control system in use. We introduce the design concept and report on the status and plans for MTCA4U.

Speaker: Martin Killenberg (DESY)

Slides mtca4u_overview_20131212.pdf

16:30 MTCA.4 developments for the ESS

The European Spallation Source is one of the largest science and technology infrastructure projects being built today. This presentation aims to provide an overview of two uTCA.4-based developments done at ESS: Timing System and Beam Current Monitor (BCM). The ESS Timing system is based on the Micro Research Finland (MRF) platform and is implemented in compactPCI and uTCA.4 form factors. A uTCA.4 timing receiver prototype was developed and integrated into the EPICS control system using the MRF EVR PMC and TEWS TAMC260 PMC carrier card. The uTCA.4 timing receiver will make use of the LVDS trigger lines in the backplane to deliver triggers to other cards. The Beam Current Monitor is based on the Struck SIS8300 fast digitizer. First version of the BCM included development of EPICS support for the SIS8300 digitizer and data processing in software. Custom SIS8300 firmware is under development to process data in hardware, which will enable fast detection of beam losses through differential current measurements.

Speaker: Mr Marko Mehle (Cosylab)

Slides ESS_SW_MTCA_2.pptx

16:45 PCIe Device Drivers Common Interface.

PCI Express is gradually gaining momentum in becoming a new industry standard for many chipset manufacturers and developers. The PCI standard is currently the most widely used architecture.However, recent industry trends indicate chipset manufacturers will also be utilizing the more afficient PCI Express chipsete in future designs, alongside the existing PCI chipsete. The uTCA as well as the majority of architectures today use the PCI Express bus as a central bus of data transmissions. In order to take full advantage of PCI Express' enhanced features, more robust device drivers are requqred. A device driver contains all the device-specific code necessary to communicate with a device. This code includes a standard set of interfaces to the rest of the system. This interface shields the kernel from device specifics just as the system call interface protects application programs from platform specifics. Application programs and the rest of the kernel need little, if any, device-specific code to address the device. In this way, device drivers make the system more portable and easier to maintain. But new devices demand new drivers and over time with increasing in number of drivers, their support is at a loss. On the other side the drivers from different producers have different API that leads to certain difficulties at the level of the user programming. However the basic functionality of the PCI Express device does not depend on device type and could be common for all drivers. The Linux Device Driver Model allows modules stacking, that basically means one module can use the symbols defined in other modules. Using the stacking and independence of the basic functionality of the PCI Express device allows us to split PCI Express device driver into multiple parts. The driver for current device will use PCI Express driver common part provided by the top level driver. The top level module provides all common structures and functions for PCI Express communication. Such flexibility will facilitate the tasks of creation and supporting of the device drivers, on the other hand it will lead to the principle ”write for one use for all” at the level of user programming. Our experience of creating and using stacked PCI Express device drivers will be presented.

Speaker: Mr Ludwig Petrosyan (DESY)

Slides pcie_driver_mtca_s.pdf

17:00 MicroTCA Module Management Controller Software

The Module Management Controller of a MicroTCA-card negotiates with the Carrier Management Controller and the Shelf Management Controller. It handles hardware signals, power load, diagnosis, receives commands. We designed a µTCA-card and used a PIC32MX460 for the MMC to develop the MMC software.

Speaker: Mr Peter Kaemmerling (Forschungszentrum Jülich, ZEA-2)

Slides Sec_MTCA_Workshop_FZJ_ZEA2_PK_MD.pdf

17:15 Considerations for the real-time performance issues in linux/MicroTCA

The MicroTCA platform has been selected for usage as the base platform for SLAC control systems for future designs and upgrades - along with embedded linux as the software platform. We have evaluated the microTCA and linux platform for usage in our timing, low-level RF, and BPM systems. We have found that the new platform brings challenges in interrupt handling, and scatter DMA. Despite migration of much of the hard real-time functionality to the FPGA firmware level, the interrupt handling and its real-time performance are important factors for our control system as the software layer needs to deterministically process time critical functions driven by each interrupt. Linux has a long processing chain for the interrupt from the kernel to user space driver, and it also provides various methods of providing the interrupt notice to the user driver: signal and ioctl() with device file. Each method provides different performance. We are going to describe our experience for interrupt handling with regard to real-time performance. In some cases DMA is also needed for applications which use fast digitizers. We have used traditional DMA for the real-time world previously, because most real-time OS(s) are based on a flat memory model. However, for linux based systems, it is not a flat memory model and we are not so lucky. We intend to use a scatter DMA engine for achieving real-time performance under linux. We have chosen the SIS8300 module from Struck for our low-level RF system and BPMs. The firmware from Struck did not support the scatter DMA, thus we had to allocate linear memory space in the kernel space for the DMA, and needed to implement a bounce buffer to copy the DMA data to the user space. This led to a lag in real-time performance. Thus, we had to implement a scatter DMA technique to avoid the bounce buffer and to allocate the DMA buffer directly into the user space. During the firmware upgrade, we learned that the following steps: configuring the DMA engine, re-arming the DMA and waiting for interrupt should be an atomic operation. In this presentation we are going to discuss the details of our software experience with interrupt handling, and scatter DMA using the MicroTCA and linux platform.

Speaker: Dr Kukhee Kim (SLAC National Accelerator Laboratory)

Slides 2013_1202_v.2_microTCA_workshop_-Real-time_performance_issues_in_linux_microTCA_platform.pdf khkim

17:30 Overview and Status of the MicroTCA for Physics Standards Effort

The effort to develop extensions to the MicroTCA standards in support of physics applications has had mixed results. Extensions to the hardware standards to define common I/O interfaces and analog signal distribution paths have defined and approved, with commercial hardware conforming to the new standards already available for purchase. Extensions to the hardware standards to provide for distribution of clocks, triggers, and interlocks are well-advanced. Both efforts have been bolstered by enthusiastic support from both a variety of lab users and a variety of hardware vendors. Extensions to software practices and standards, however, have been stymied by a relative dearth of support from lab users and by the self-limiting of industry participation largely to the role of observer. One guideline, for a common device access framework, has been drafted and a first-pass reference implementation has been created; however, further progress has been halted due to a lack of application-oriented test and review. A draft guideline for a standard process model has been half-completed, but completion and prototyping are on hold pending availability of a willing author/implementer with EPICS expertise. Other guidelines and prototypes have also stalled for lack of authors and implementers. The Software and Protocols committee is issuing a plea for lab participation in the software standards effort.

Speaker: Dr Dariusz Makowski (Lodz University of Technology, Department of Microelectronics and Computer Science)

Slides Software&Protocols_SLAC_20130722.pdf

17:45 → 18:00 Closing remarks

Speaker: Dr Holger Schlarb (DESY)

18:00 → 19:00 DESY Tour 4