4th MicroTCA Workshop for Industry and Research

Europe/Berlin
CFEL (DESY)

CFEL

DESY

Building 99, Notkestraße 85, 22607 Hamburg
Holger Schlarb (DESY) , Kay Rehlich (DESY)
Description

The 4th MicroTCA workshop for industry and research will take place from 9th to 10th December 2015 at DESY in Hamburg, Germany. DESY invites you to participate in this workshop.

The registration fee is 150 € per person including coffee and lunch breaks, DESY/XFEL tour, workshop dinner and workshop materials.

Campus Map
Participants
  • Adam Kutynia
  • Aleksander Mielczarek
  • Aleksander Szubert
  • Alexander Menshikov
  • Alexander Schnase
  • Aljaz Dobnikar
  • Anders Johansson
  • Anders Svensson
  • Andre Gössel
  • Andriy Ushakov
  • Annika Rosner
  • Anushavan Azatyan
  • Aram Kalaydzhyan
  • Armin Reichold
  • Attila Hidvegi
  • Axel Neumann
  • Balazs Szalai
  • Bartosz Ostrowski
  • Ben Slaghekke
  • Borut Repic
  • Brian Axbog
  • Brian Ulskov Sorensen
  • Bruno Fernandes
  • Cesar Carpinteiro
  • Christian Gruen
  • Christian Schmidt
  • Christian Ther
  • Christoph Stechmann
  • Dariusz Makowski
  • Davit Kalantaryan
  • Dimitri Tischhauser
  • DongCheol Shin
  • Endric Schubert
  • Enrico Braidotti
  • Ewa Janas
  • Frank Babies
  • Frank Ludwig
  • Frank Storm
  • Frank Tonisch
  • Fredrik Kristensen
  • Friedrich Fix
  • Gerhard Schleßelmann
  • Gerrit Hesse
  • Giil Kwon
  • Gohar Ayvazyan
  • Gregor Wittig
  • Grzegorz Daniluk
  • Guillaume Renaud
  • Guy Laszlo
  • Hamed Sotoudi Namin
  • Hans Henningsen
  • Heiko Körte
  • Heinz Hartmut Ibowski
  • Henning Weddig
  • Holger Kay
  • Holger Schlarb
  • Ian Shearer
  • Igor Rutkowski
  • Ingmar Hartl
  • Ingo Martens
  • Isa Uzun
  • Jan Marjanovic
  • Jana Raabe
  • Jasmin Goelzenleuchter
  • Jens Zappai
  • Johan Fopma
  • Johannes Tempel
  • John McLean
  • John Molendijk
  • Jonathan Hollar
  • Juergen M. Jaeger
  • Jukka Pietarinen
  • Julian Mendez
  • Julien Branlard
  • Karl Judex
  • Kay Klockmann
  • Kay Rehlich
  • Ki-Hyun Kim
  • KiSu Eom
  • Konrad Przygoda
  • Kristian Harder
  • Krzysztof Czuba
  • Krzysztof Nikliborc
  • Kwinten Nelissen
  • Lara Lloret Iglesias
  • Laurent WEBER
  • Lee Taekoo
  • Lee Woongryol
  • Lorenzo Pivetta
  • Luca Federici
  • Ludwig Petrosyan
  • Lukasz Butkowski
  • Maciej Grzegrzółka
  • Malcolm Locke
  • Manuel Mommertz
  • Marcin Kiepiela
  • Mariusz Grecki
  • Mariusz Mróz
  • Markus Hübsch
  • Martin Killenberg
  • Martin Konrad
  • Martin Tolkiehn
  • Mathieu Omet
  • Matthias Balzer
  • Matthias Drochner
  • Matthias Felber
  • Matthias Hoffmann
  • Matthias Kirsch
  • Matthias Werner
  • Michael Abbott
  • Michael Fenner
  • Michael Heuer
  • Michael Kuntzsch
  • Michael Neumann
  • Michael Oelmann
  • Michael Rieck
  • Nadeem Shehzad
  • Nicolas Detrez
  • Niels Koll
  • Nigel Forrester
  • Norman Kranich
  • Ofir Shefer Shalev
  • Olaf Hensler
  • Pablo Echevarria
  • Pavel Bastl
  • Pawel Plewinski
  • Peter Goettlicher
  • Peter Johnston
  • Peter Milne
  • Petr Pivonka
  • Petr Vetrov
  • Piotr Miedzik
  • Piotr Perek
  • Qingqing Xia
  • Radoslaw Rybaniec
  • Rafael Baron
  • Rainer Görgen
  • Rainer Susen
  • Ralf Waldt
  • Raymond Larsen
  • Reinhard Steinbrück
  • Remigiusz Danych
  • Roland Winteler
  • Ruben Aszkenasy
  • Rudi Ganss
  • Rüdiger Cölln
  • Scott Robson
  • Simone Farina
  • Sven Karstensen
  • Szymon Jablonski
  • Takemasa MASUDA
  • Thoirsten Kracht
  • Thomas Decker
  • Thomas Holzapfel
  • Thomas Weber
  • Thorsten Lamb
  • Tim Wilksen
  • Timmy Lensch
  • Tino Häupke
  • Tino Lang
  • Tobias Hoffmann
  • Tobias Poethig
  • Tomasz Jezynski
  • Tomasz Kozak
  • Tomasz Wlostowski
  • Uros Mavric
  • Vahan Petrosyan
  • Valeri Ayvazyan
  • Vincent Bobillier
  • Vollrath Dirksen
  • Wojciech Cichalewski
  • Wojciech Jalmuzna
  • Yousef Rahnavard
Support
    • 14:00 17:00
      Integration Workshop 3h BAH1/BAH2, Building 3 (DESY Hamburg)

      BAH1/BAH2, Building 3

      DESY Hamburg

    • 10:00 13:00
      Integration Workshop 3h BAH1/BAH2 (Building 3, DESY Hamburg)

      BAH1/BAH2

      Building 3, DESY Hamburg

    • 13:00 14:00
      DESY/XFEL Tour 1 1h in front of building 3 (DESY Hamburg)

      in front of building 3

      DESY Hamburg

    • 14:30 17:30
      Tutorials by experts BAH1/BAH2 (Building 3, DESY Hamburg)

      BAH1/BAH2

      Building 3, DESY Hamburg

      • 14:30
        MicroTCA.4 Tutorial Basics 45m
        Speaker: Mr Dietmar Mann (Schroff GmbH)
      • 15:15
        MicroTCA Management 45m
        Speaker: Christoph Stechmann (DESY)
      • 16:00
        Tutorial about MicroTCA.4 45m
        Speaker: Mr Vollrath Dirksen (N.A.T. GmbH)
        Slides
      • 16:45
        MTCA and PCI Express and PCI Express Hot Swap under Linux 45m
        Speaker: Mr Ludwig Petrosyan (DESY)
        Slides
    • 08:30 09:00
      Registration 30m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
    • 09:00 09:15
      Welcome 15m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
    • 09:15 10:30
      Session 1 CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Convener: Raymond Larsen (SLAC)
      • 09:15
        Follow up on HVF "MicroTCA.4 for Industry" and Workshop Introduction 15m
        Speaker: Holger Schlarb (DESY)
        Slides
      • 09:30
        Keynote: All programmable: Current development and future trends in the world of FPGAs 45m
        Speaker: Michael Oelmann (Xilinx)
        Slides
      • 10:15
        The large Scale European XFEL MicroTCA Installation 15m
        The European XFEL is in the final construction and commissioning phase at DESY. This 3.4 km long facility will be equipped with more than 200 MicroTCA crates. First parts of this installation are already in operation. An overview of this complex system will be presented.
        Speaker: Kay Rehlich (DESY)
        Slides
    • 10:30 11:00
      Coffee &Poster 30m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
    • 11:00 12:30
      Session 2 CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Convener: Mr Dietmar Mann (Schroff GmbH)
      • 11:00
        Status and Experience with MicroTCA.4 LLRF systems at DESY 15m
        Since 2011 several facilities within DESY have been upgraded with a MicroTCA.4 based LLRF system. This includes FLASH, RAGAE, PITZ and the XFEL injector. These systems are in permanent operation and provide high quality RF regulation system to its users. This talk summarizes the activities ongoing and the future upgrades, as well as the operational experiences and lessons learned from failures.
        Speaker: Mr Christian Schmidt (DESY)
        Slides
      • 11:15
        MicroTCA.4 at FRIB 15m
        The Facility for Rare Isotope Beams is planning to use MTCA.4-compatible hardware for several systems. This talk presents the status of the development of these applications. A cornerstone of this approach is our general purpose FPGA board which has been developed for modular applications in MTCA.4 chassis as well as low-cost pizza box devices. We will also present an open-source application for generating FRU EEPROM data that can be integrated easily into a Continuous Integration workflow.
        Speaker: Dr Martin Konrad (Facility for Rare Isotope Beams)
        Slides
      • 11:30
        MicroTCA Image Processing System at SPring-8 15m
        We have evaluated MicroTCA as a candidate of the next-generation front-end controller since 2011. As the first application, we have developed a MicroTCA-based image processing system for electron beam diagnostics of the SPring-8 accelerators. In order to realize rapid development, it was built with commercial off-the-shelf products such as a Camera Link FMC, an FPGA AMC with FMC slot and a processor AMC. The Camera Link IP core on the FPGA AMC was newly developed in compliance with the AXI4 open-bus. We will present the details of the implementation. In addition, the plan of the new system using MicroTCA.4 will be introduced.
        Speaker: Dr Takemasa MASUDA (JASRI/SPring-8)
        Slides
      • 11:45
        MicroTCA.4 BPM system at CRYRING@ESR 15m
        GSI Helmholtz Centre for Heavy Ion Research is developing a BPM system for CRYRING@ESR - the heavy ion storage ring formerly located at Stockholm University. The base platform in AMC/MicroTCA.4 and ANSI/VITA FMC form factors was developed by Warsaw University of Technology and is being modified deeply by GSI to include FESA and WhiteRabbit support. This presentation describes the process of development and integration of: - FPGA firmware for AFC board that is used as the digital back-end for BPM digital signal processing and orbit feedback in a processing node - MicroTCA.4 WhiteRabbit receiver node - RTOS-based MMC firmware with an additional task included to avoid implementing the soft microprocessor in FPGA This presentation also describes additional tools developed to debug and verify the system.
        Speaker: Mr Piotr Miedzik (GSI)
        Slides
      • 12:00
        Status of MTCA at Korea Superconducting Tokamak Advanced Research (KSTAR) facility 15m
        The KSTAR device is a medium-size, D-shaped tokamak with the major machine parameters of R = 1.8m, a = 0.5m, B = 3.5T, Ip = 2 MA, κx = 2.0 and δx = 0.8. Its main research goal is to demonstrate the steady-state operation in the high-performance, advanced tokamak (AT) modes. The KSTAR Integrated Control System (KICS) is composed of various heterogeneous controllers, and it is a networked-based distributed control system based on EPICS. All possible open source tools such as MDSpluse, Qt, MySQL, etc. are integrated inside KICS. Since the first campaign, lots of control systems are annually developed and installed. Now, KSTAR operation has entered into the second phase. It means high-efficient plasma is generated for longer period. We consider the MTCA platform as a basic real time control system environment. Modulized standard components will be implemented for the next decade campaign. This presentation describes the current work of the MTCA based control system at KSTAR. We also introduce the activity of customized digital control systems for the plasma diagnostics.
        Speaker: Dr Woongryol Lee (National Fusion Research Institute)
        Slides
      • 12:15
        European XFEL Detector and DAQ related hardware and firmware developments 15m
        The European X-Ray Free-Electron Laser facility (European XFEL) will generate intense ultra short coherent X-Ray flashes spaced by 220 ns and each with a width of less than 100 femtoseconds. They are group into trains of up to 2700 pulses within 600 us with a 10 Hz repetition rate. Bandwidths of 10 GBytes of data per second are expected from upcoming 2D pixel detectors, while other detector types, like systems based on fast digitizing analog-to-digital converters, can go up to 60 MBytes per channel. To meet these requirements, the European XFEL Advance Electronics group is developing, in-house or in collaboration with external institutes, solutions within the MicroTCA.4 and AdvancedTCA standard. Advances are being made in a wide range of fields including guidelines for FPGA development, assemble and process of data from large-area 2D image detectors, fast digitizing of pulse signals with algorithms for peak and energy detection, low latency communication protocol for VETO systems, to a high-level FPGA programming framework for users unfamiliar with HDL. In this contribution, a summary of all developments that have been taken place in the European XFEL is presented together with the future steps and objectives.
        Speaker: Mr Bruno Fernandes (European XFEL)
        Slides
    • 12:30 14:00
      DESY/XFEL Tour 2 and 3 1h 30m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
    • 12:30 14:00
      Lunch 1h 30m DESY Hamburg

      DESY Hamburg

    • 14:00 15:45
      Session 3 CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Convener: Mr Ian Shearer (VadaTech Ltd)
      • 14:00
        AdvancedMC usage in adjacent industries 15m
        The presentation will provide an update on the reasons why AdvancedMCs are being chosen for use in adjacent industries in order to give a better appreciation of the features that can be leveraged by the physics community. In particular, there has been a growing need to cluster AdvancedMC based processors and make them easier to setup and use which could be appropriate. The presentation will provide examples from wireless test and edge based high performance computing to illustrate real life configurations and demonstrate that a single core design can easily be reused.
        Speaker: Mr Nigel Forrester (Concurrent Technologies)
        Slides
      • 14:15
        Using building blocks offers a high variety of possible chassis configurations 15m
        Different members in the physics community do have different requirements on MTCA.4 crates. Schroff is working with building blocks in order to meet the individual requirements by using standard components. The presentation shows examples, how these individual solutions were developed by using building blocks. Further we want to introduce essential accessories like front- and filler panels and of cause our AMC covers. Also supplementary products like our cabinets with air-to-water cooler are mandatory to ensure a proper environment.
        Speaker: Mr Rüdiger Cölln (Pentair Technical Solutions GmbH)
        Slides
      • 14:30
        New developments and designs for MTCA.4 by eicSys 15m
        eicSys is a license partner for some Boards developed by DESY. Additional to these boards eicSys developed new boards for MTCA.4 and increased the productportfolio for MTCA.4 application. The reason for the eicSys product expansion is to bring MTCA.4 closer to industry requirements with high end performance.
        Speaker: Mr Friedrich Fix (Eicsys Embedded Integrated Control Systems)
        Slides
      • 14:45
        New SP Devices MTCA Digitizers designed for medium speed applications in Physics 15m
        Signal Processing Devices DAQ MTCA.4 offering for demanding applications in Physics is focussed on: • high vertical resolution . high speed digitizers needs • extended real time data processing
        Speaker: Mr Laurent Weber (Signal Processing Devices AB)
        Slides
      • 15:00
        Medium Speed IO on Micro TCA 15m
        KMCU, a new AMC module and Micro TCA.4 RTM brings a wide range of simultaneous analog IO to Micro TCA. The AMC module, featuring a ZYNQ system on chip includes one FMC site, while the RTM carries two analog modules from the D-TACQ range, based on a subset of FMC. The combination can provide from 4..64 channels of medium speed Analog IO, with capability for local processing and connectivity on PCI-Express, Ethernet and SFP/Aurora links. The presentation will provide a brief overview of the AMC module, and the analog module range. Separately, a live demo will be available.
        Speaker: Mr Peter Milne (D-TACQ Solutions Ltd)
        Slides
      • 15:15
        AMC-RF Source up to 1400 MHz 15m
        Overview on the development of an AMC-RF Source from 10 MHz to 1400 MHz
        Speaker: Mr Norman Kranich (SINTEC Microwave Systems GmbH)
        Slides
      • 15:30
        The SIS8800 Multi Purpose MTCA.4 Scaler AMC and the SIS8980 Discriminator RTM 15m
        Multi Channel Scaling (MCS) capability is essential for many Physics related applications. Counter based beam loss monitor (BLM) systems and Synchrotron beamline instrumentation are just two examples. The 16 -front panel- channel SIS8800 multi purpose counter board was developed with the GSI FAIR LASSIE BLM as the first use case in mind. Another 16 scaler channels are available over the associated SIS8980 discriminator RTM. Other future associated RTMs -possibly making more use of the full available IO count and/or MGTs- will be addressed in the outlook.
        Speaker: Dr Matthias Kirsch
        Slides
    • 15:45 16:15
      Coffee 30m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
    • 16:15 18:00
      Session 4 CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Convener: Mr Thomas Holzapfel (industrie partner)
      • 16:15
        Simplify JTAG debugging with JTAG Switch Module for MTCA systems 15m
        The NAT-JSM is an MTCA compliant JTAG switch module. It’s flexible design makes it compatible with most of todays MTCA chassis providing a JSM slot. Miss-Insertion protection The module detects whether it is inserted into an AMC, MCH or JSM slot. Only if a JSM slot is detected the output drivers are turned on. The only prerequisite for miss-insertion protection is that the pinout of the connector follows the basic rules of the AMC connector. Flexible Pinout The JSM module can be adapted to nearly any existing JSM system connector by configuration of the onboard FPGA as long as it is based on the AMC connector layout. Auto configuration versus manual configuration By default the JSM module automatically arbitrates the JTAG master port and the slave port is selected by the TAP controller. The automatic configuration can be overruled at any time by manual configuration through front panel elements. Key Features: - JTAG download from MCH via WEB Interface - JTAG programming connector at front panel - Automatic arbitration between JTAG Masters - Target selection through JTAG information - Overrule of automatic operation and dedicated selection of JTAG target by front panel elements - Multiple JSM Pinout configurations via FPGA - Power supply through MCH power channels or power module SMP power - Minimal power consumption
        Speaker: Mr Vollrath Dirksen (N.A.T. GmbH)
        Slides
      • 16:30
        Extension Management for MTCA.4 15m
        Extension of management of MTCA.4 to address new enhancements
        Speaker: Mr Vollrath Dirksen (N.A.T. GmbH)
        Slides
      • 16:45
        Detector Applications on MicroTCA.4 Platform at CAEN ELS 15m
        The AMC-PICO-8 and HV-PANDA boards will be presented as well as their complementary role as a high voltage bias source and low-current measurement system will be discussed. Various different applications which can benefit from the combined system will be demonstrated. The AMC-PICO-8 is a modular system, composed by a DAMC-FMC25 board and two FMC-PICO-1M4 plug-ins; customization of analog front-ends to suit the user's needs will also be shown. A detailed overview of the data acquisition system with an advanced DMA controller, Linux driver and Oscilloscope application will be given.
        Speaker: Jan Marjanovic (CAEN ELS)
        Slides
      • 17:00
        Next step in PCI-ExpressFabric Switching 15m
        How can MTCA.4 systems benefit from the new features of PCI-ExpressFabric technology announced by Avago? The Avago PEX9700 series switch chips with ExpressFabric technology offer an industry-suite of new features that dramatically improve performance while reducing power consumption and cost by 50% for the most demanding hyper-converged, NVMe, and rack scale systems. Key Features: * Enable Multi-Node cluster over PCIe Fabric * Host-to-Host DMA * Share I/O Among Multiple Hosts * Dedicated x1 PCIe port for switch management * Downstream Port Containment (DCP / eDPC) * SSC Isolation and SRIS Clocking * No Changes to Existing Standard Software & Drivers
        Speaker: Mr Heiko Körte (N.A.T. GmbH)
        Slides
      • 17:15
        2800 MB/s Heterogeneous Data Processing for a 4-channel, 5.6 Gbps Wind-LIDAR-System 15m
        The bistatic Wind-LIDAR-System developed by German Physikalische-Technische Bundesanstalt (PTB) is a great practical example on how MicroTCA systems can solve computational challenges: With 4 analog channels, each sampled at 350M samples per second with 16 bits per sample, 2800 MB/s of streaming data can be tackled with heterogeneous compute elements. As a first-stage data processing instance we selected an FPGA, a Xilinx Virtex-7 690T with multiple high-speed SerDes interfaces. The targeted measuring principle requires a deterministic latency between the generated waveforms sent to the DACs and the corresponding input data. This is guaranteed by using the JESD204B protocol to transfer the data between the FPGA and the ADC/DAC. Our presentation will elaborate on the design choices and observations when using JESD204B within an FPGA environment. The FPGA has the task to essentially reduce the data rate and to transport the data to the DSPs, TMS320C6678 from TI, for subsequent data analysis. In our presentation we will highlight the custom signal processing implemented inside the FPGA which effectively reduces the data rate down to 50M samples per second with 32 bits per sample, per channel. Data transmission from the FPGA to the multi-DSP subcomponent is done via PCIe Gen3 x4 at 200MB/s per channel. We will demonstrate how we used a MicroTCA backplane for PCIe and go into details of a custom protocol on top of PCIe which mimics the queue aspects of modern NVMe SSDs to reduce latency and implementation effort. We will then discuss the architecture of three separate DSP, two DSP for further processing per channel followed by overall processing done in the third DSP, again reducing the amount of data. The DSP themselves are interconnected via PCIe Gen2 x2, the third DSP also connects via Gigabit Ethernet on the MicroTCA backplane to transport data at the final rate of 20MB/s to a PC component featuring an Intel i7 CPU. Finally, Ethernet on the MicroTCA backplane is used for system-wide setup and control.
        Speaker: Mr Karl Judex (Industry)
        Slides
      • 17:30
        Image acquisition and processing with MicroTCA.4 15m
        Development of high-performance digital cameras in recent years has made them promising tools for observing transient and fast events in large-scale scientific experiments. The modern digital cameras allows grabbing images with a megapixel resolution and thousands frames per second. A digital camera working with a high resolution and a high frame rate produces a large stream of data reaching dozens of gigabytes per second. A precise nanosecond synchronization is also requires to record a dynamic processes in physics applications. A flexible and powerful hardware platform is required for image acquisition and image processing in real time. The MicroTCA.4 standard, originally developed for the High Energy Physics community, provides all required interfaces to design a powerful and scalable image acquisition system. The MicroTCA.4 chassis accommodates a few frame grabber modules, synchronization card and provides high-throughput interfaces and trigger signals on its backplane. The presentation shows the requirements and architecture of image acquisition systems designed with MicroTCA.4 standard. The image acquisition system is composed of frame grabber module with Camera Link interface, precision timing module and CPU. The developed software framework currently supports cameras from three vendors: Microtron, PCO and Andor.
        Speaker: Dr Dariusz Makowski (Lodz University of Technology, DMCS)
        Slides
      • 17:45
        A versatile MicroTCA timing system used at the European XFEL 15m
        This presenstation will demonstrate the advantages of using MicroTCA for the timing system at the European XFEL. Benefits for end-user applications will be presented and a few examples on how trigger and clock signals of AMC modules are connected and configured in the current setup will be shown. A special attention will be given to the versatility of the NAMC-psTimer provided by NAT.
        Speaker: Christoph Stechmann (DESY)
        Slides
    • 19:00 23:00
      Workshop Dinner at Villa Mignon 4h Osdorfer Landstraße 380 (Hamburg)

      Osdorfer Landstraße 380

      Hamburg

    • 09:00 10:30
      Session 5 CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Convener: Enrico Braidotti (CAEN ELS)
      • 09:00
        MTCA.4 based LLRF for the European Spallation Source 15m
        The European Spallation Sourse, or ESS, is a 5 MW neutron source being built in Lund, Sweden. The proton Linac that generates the beam to produce the neutron is pulsed at 14 Hz, and the design is beam loss limited. This gives fairly strong requirements for the RF systems, including the LLRF regulation off the cavity fields. The talk will give an overview of the design and status of the ESS LLRF system, which is based upon MTCA.4.
        Speaker: Dr J Johansson Anders (European Spallation Source, Lund University)
        Slides
      • 09:15
        MTCA.4 at ELI Beamlines - status and plans 15m
        ELI Beamlines (Extreme Light Infrastructure) is newly emerging petawatt-class laser facility currently being constructed in the Czech Republic as a part of EU effort to build a new generation of large research facilities. ELI constellation includes another two facilities: ELI Attosecond in Hungary and ELI Nuclear Physics in Romania. The decision was made to employ the MTCA.4 hardware platform widely in various applications inside both the laser beam distribution subsystem and experimental chamber's secondary sources and target setups at ELI Beamlines. Covered tasks dedicated to MTCA.4 are to be: adaptive optics, laser beam alignment, temporal and spatial synchronization of multiple femto-second pulse laser beamlines, and beamlines common diagnostics. The talk on behalf ELI Beamlines Control Systems group presents the ideas and concepts of these MTCA.4 applications at ELI Beamlines and the current status of their preparatory phase.
        Speaker: Mr Petr Pivonka (ELI Beamlines)
        Slides
      • 09:30
        Mezzanine style RTMs – a simple route towards your own custom MTCA.4 signal conditioning 15m
        The MTCA.4 standard and its growing market provides the physics community with a high performance replacement for ageing standards such as VME. As highly performant, flexible and programmable FPGA based digital elements and variable data transfer methods are now readily available in the MTCA.4 standard, many institutions can focus their custom electronics developments more closely onto aspects that are truly specific to their experimental needs. However, the threshold for starting a first MTCA.4 development is still significant as groups have to understand the standard and adhere to its stringent and sometimes complex demands and follow the rapid developments in the FPGA market. To lower this threshold and to get started with our first MTCA.4 project the particle physics sub-department at the University of Oxford has decided to co-develop a pilot project together with VadaTech and Etalon AG. The project aims to realise a signal conditioning unit for high speed interferometric applications. It provides variable gain, bandwidth and coupling to single mode optical inputs in the 1550nm range in the form of an MTCA.4 rear transition module designed to work with VadaTech’s AMC523 units. To maximise the usefulness of our developments to other developers we use a mezzanine configuration in which the base unit of the RTM will be designed to accept a wide range of mezzanine boards. The mezzanine itself is entirely focussed on the signal conditioning functions and can be realised with very little prior knowledge of the MTCA.4 standard by adhering to the electrical and mechanical interface specifications with the associated base unit. As the project is only 2 months old we will present the scientific and commercial motivation and applications of these boards, show initial specifications and the mezzanine Ansatz and explain why and how we expect this development approach to be expanded towards other applications at the department of Physics in Oxford.
        Speaker: Armin Reichold (Oxford University, department of Physics)
        Slides
      • 09:45
        MicroTCA.4 based laser pulse controller for the injector laser at FLASH and XFEL 15m
        The user facility FLASH is a multi-beamline free electron laser (FEL) which means that, at FLASH, a common superconducting injector LINAC drives two separated undulator beamlines. A normal conducting laser driven RF-gun produces the electron bunches. In order not to limit the parameter ranges the tuning possibilities for both electron beams have to be the same. Therefore the electron bunches for the different undulator beamlines are being produced by two different injector lasers. A third laser system is available to produce ultra-short electron bunches. To fulfill these requirements and to drive the injector laser a new MicroTCA based laser pulse controller has been developed. This talk will explain how the laser controller works and which MicroTCA resources (hardware and software) have been used for the development. It will also give an overview about the communication handling between the laser system and peripheral MicroTCA systems. Since 2015 the same system controls the injector LASER at the European XFEL facility.
        Speaker: Mr Christian Gruen (DESY)
        Slides
      • 10:00
        PICMG activities, new and future standards 15m
        Speaker: Mr Heiko Körte (N.A.T. GmbH)
        Slides
      • 10:15
        Report on Status of MTCA.4 Standards Extensions for Physics 15m
        The two PICMG (PCI Industrial Computer Manufacturers Group) working groups have been successful in 2015 at completing comprehensive drafts for new hardware extensions based on the auxiliary Rear Transition Module Backplane and supporting modules, and near-completion of four Software Guidelines. The design features, status and next steps to PIMCG approval will be described briefly.
        Speaker: Mr Ray Larsen (SLAC)
        Slides
    • 10:30 11:00
      Coffee & Poster 30m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
    • 11:00 12:30
      Session 6 CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Convener: Mr Matthias Balzer (KIT)
      • 11:00
        Keynote: RapidIO 20-50 Gbps technology for data acquisition and analytics 30m
        Speaker: Ruben Aszkenasy (IDT)
        Slides
      • 11:30
        xTCA evaluation project status report and HPM modules development at CERN 15m
        MicroTCA and AdavancedTCA are the selected platforms for the upgrade of the back-end electronics of some Large Hadron Collider (LHC) experiments at CERN. In this context, the CERN PH-ESE group launched in 2011 to perform technical evaluations of xTCA equipment with the focus on infrastructure components. The aim is to issue technical recommendations to the experiments and provide support for selected equipment. Following the MicroTCA technical evaluation phase, specifications were written for a custom vertically cooled shelf and a power module. Finally an official price enquiry was launched. After manufacturer selection, qualification tests were carried out to assess the selected products characteristics: cooling and backplane quality of the MTCA shelves as well as regulation, efficiency, ripple/noise and standard compliance of the power modules. The same procedure has started for ATCA, with particular focus on the shelves in-rack cooling evaluation. In parallel to these activities CERN is implementing significant MMC code enhancements: xTCA standard compliance, user customization and multi-platform versatility. The MMC source code is now divided in 3 parts: an application core, containing the standardized features, a driver directory, implementing the MCU dependant low level functions and a user part easing the code customization. This new architecture allowed porting the program to a 32bit microcontroller used at CERN and will future-proof the code for upgrades. This presentation will give an overview of the xTCA evaluation project with the qualification test procedure and the results obtained with the selected MTCA equipment. It will also give a brief overview of the on-going activities on the ATCA front. Additionally, an overview of the hardware platform management modules developed at CERN will be given, including the new MMC open-source package.
        Speaker: Mr Julian Mendez (CERN)
        Slides
      • 11:45
        Production and in-system programming of MicroTCA boards 15m
        Hardware installation for European XFEL is a huge logistical challenge, since hundreds of boards have to be tested, programmed, maintained and serviced. DESY MSK department provides and uses an automated approach for programming MicroTCA boards - for post-production-programming and for in-field-update of all on-board memories. These are the key aspects: 1. Automated management programming: DESY has developed a method for script-based programming of MMC, Bootloader, FRU, and Chip fuses 2. Automated FPGA programming: DESY provides a command-line tool for generation of HPM files - for both MMC and FPGA bit files. If DESY MMC V1.00 is used, the upload process can be shortened significantly due to usage of a proprietary bitstream compression. 3. Toolchain integration: The software build tools are scripted. The version number is taken from version control system via pre-build-scripts and is automatically placed into the firmware images, making it possible to query version number via IPMI tool and trace changes according the DESY version control system (SVN). Post-build scripts automatically generate directly uploadeable HPM files. 4. In-field update: All memories can be programmed via IPMItool, allowing remote update of all stations. The methods, tools and scripts are presented. They are available to DESY licensees.
        Speaker: Michael Fenner
        Slides
      • 12:00
        MicroTCA.4 based single cavity regulation including piezo controls 15m
        We want to summarize the single cavity regulation with MTCA.4 electronics. Presented solution is based on the one MTCA.4 crate integrating both RF field control and piezo tuner control systems. The RF field control electronics consists of RTM for cavity probes sensing and high voltage power source driving, AMC for fast data processing and digital feedback operation. The piezo control system has been setup with high voltage RTM Piezo driver and low cost AMC based FMC carrier. The communication between both control systems is performed using low latency link over the AMC backplane with data throughput up to the 3.125 Gbps. First results from CW operation of the RF field controller and the cavity active resonance control with the piezo tuners are demonstrated and briefly discussed.
        Speaker: Mr Radoslaw Rybaniec (DESY)
        Slides
      • 12:15
        RTM-Modules for waveform digitization. 15m
        Digitization of signals is often an important issue of electronics of experiments. Most of the waveform digitizers are built on pipelined ADCs sampling signal of interest. An alternative state of the art solution for the conversion of short signals at GHz rate is based on capacitor arrays. We designed two signal digitizers using those two concepts. The first module is a 16-channel waveform digitizer based on four DRS-4 capacitor arrays. The DRS-4 is able to sample simultaneously 9 signals with a frequency from 700MHz to 5GHz. Every channel of the module is equipped with a comparator for self-triggering. Upon a trigger the signals recorded in the pipelines are converted with 12-bit multichannel ADCs at 30MHz. During digitization the pipelines of another DRS-4 are used for sampling signals to minimize the dead time. One pipeline of each capacitor array is used for producing a sub nanosecond time tag of recorded signals. The second module is a 32-channel ADC board. Each channel of the module is equipped with individually adjustable variable gain amplifiers and 5th order antialiasing filters. Four 8-channel ADCs digitize signals at frequency from 10 to 40MHz. Both modules are built as RTM modules according to MTCA.4 specifications. They follow the Zone-3 pin assignment recommendation from MTCA.4 community at HGF.
        Speaker: Mr Alexander Menshikov (KIT)
        Slides
    • 12:30 14:00
      DESY Tour 4 and DESY Tour 5 1h 30m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
    • 12:30 14:00
      Lunch 1h 30m CFEL (DESY Hamburg)

      CFEL

      DESY Hamburg

    • 14:00 15:45
      Session 7 CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Convener: Julien Branlard (DESY)
      • 14:00
        RTM Backplane Extension for the MTCA.4 Standard 30m
        The idea of the RTM Backplane was originally created to simplify cable management of an MTCA.4 based LLRF control system for the European XFEL project. The first RTM backplane (called an RF Backplane) was designed to distribute about dozen of precise RF and clock signals to uRTM cards. It was quickly found out, that this backplane offers very powerful extension possibilities for the MTCA.4 standard and can be used also more widely than for the RF applications only. Additionally it found significant interest in the MTCA.4 community. This contribution describes the joint effort put in working out the entire RTM Backplane extension: starting from the design of high-performance backplane PCB able to distribute tens of clock and RF signals (DC to 6 GHz) together with low noise power supply and data transmission, going through mechanical integration with crates and development of management and rear power supply solutions that do not violate the MTCA.4 standard, ending on description of a huge effort of the PICMG hardware team that further developed and put the RTM Backplane concept into the formal frames of PICMG document. Additionally, the most important features of the RTM Backplane extension will be described together with the effort of creating the final, PICMG standard compatible RF Backplane version for the E-XFEL project.
        Speaker: Dr Krzysztof Czuba (ISE, Warsaw University of Technology)
        Slides
      • 14:30
        EMC Test Adapter for MTCA.4 Modules 15m
        In MTCA.4 systems sensitive analogue and aggressive digital signals have to be handled within the crate that is equipped with modules designed by multiple designers for multiple purposes. Each of these modules introduces noise mainly by conductive coupling into the ground system. In highly sensitive systems only modules should be used that have been classified to have minor impact on the noise budget. For a proper classification of the modules a reliable test procedure has to be developed. Key part of this procedure is a test setup that can measure the board characteristics without the influence of other system components with special attention to the isolation of the ground system. A first sample of a test adapter has been developed. Details of the design and first measurement results will be reported.
        Speaker: Dr Heinz Hartmut Ibowski (b1 Engineering Solutions GmbH)
        Slides
      • 14:45
        High precision analog measurements in high speed modular standards 15m
        One of the major benefit of a MicroTCA.4 system is to combine high-speed digital data processing AMC boards with high precision analog signal conditioning RTM boards. In this presentation we show high precision measurements using different grounding configurations, particularly for AMC and RTM Z3 ac-coupled differential signal transmission for the detection and regulation of high frequency signals and broadband dc-coupled signal conditioning on RTMs. We present EMC concepts, sources of distortions, detectors signal purity, its channel scaling behavior, signal integrity and the packaging required for measurements far below -80dB. In addition we compare the partitioning of high precision sub-components in modular standards and its impact on the robustness and reliability for the operation.
        Speaker: Dr Frank Ludwig
        Slides
      • 15:00
        AMC and RTM Boards Intended for Performance Evaluation of MTCA.4 Based Modules 15m
        In this contribution a pair of two MTCA.4 based modules, AMC and RTM, is presented. These boards allow to evaluate the performance and check the functionality of all MTCA.4 based modules compliant with Analog Class Recommendation A1. Both modules feature 10 analog feed-through channels working with frequencies up to 3 GHz and low noise clock distribution circuit. The AMC module features also 5 high speed DACs and optional Kintex 7 FPGA module with PCI Express connectivity. The concept, design and performance of these modules will be presented.
        Speaker: Mr Maciek Grzegrzółka (Warsaw University of Technology, ISE)
        Slides
      • 15:15
        FPGA-Based Hardware Accelerators for 10/40 GigE TCP/IP and Other Protocols 15m
        FPGA in MicroTCA systems not only offer efficient implementations of various I/O interfaces. FPGA cards can also serve as high-performance, low-latency and low-power data processors to offload compute intensive tasks from CPUs. Today's networking protocol implementations typically are software-based and, therefore, exhibit milliseconds of latency. At the same time, the packet handling puts a high load onto the CPU. At line rates of 10 GigE, or faster, this limits performance and causes additional latencies. TCP/IP Offload engines which are state-of-the-art in server technology offer help and, with the advent of programmable SoCs and FPGAs, become feasible for MicroTCA systems acceleration. We will introduce a new technique that uses hardware-acceleration of networking protocol stacks, specifically targeted for MicroTCA Systems. By being able to optimize for a specific application and its underlying network protocols, we can go beyond a state-of-the-art TCP/IP Offload Engine (TOE) and, thereby, can reach userspace latencies faster than 1 microsecond and be much closer to the theoretical bandwidth limits. Typically, to the implementor the burden is the significant efforts when implementing Network protocols in VHDL or Verilog. However, High-Level Synthesis, where an FPGA can be designed starting from a C, C++, or SystemC description, recently became a very valid and efficient design flow option. Our talk focuses on methodologies suitable for protocol and streaming media designs and how to use automatic synthesis of interfaces such as AXI-4 Lite and AXI-4 Stream Interfaces, or simple FIFO and Memory access.
        Speaker: Dr Endric Schubert (Missing Link Electronics)
        Slides
      • 15:30
        SLAC National Accelerator Laboratory MicroTCA.4 Collaboration 15m
        SLAC National Accelerator Laboratory has two microTCA collaborations with other laboratories. These collaborations are to developed BPM systems with European Spallation Source (ESS) and Pohang Accelerator Laboratory (PAL). The ESS collaboration is designing a new Rear Transition Module (RTM) that can be used as a BPM interface and as a LLRF interface for a development system. The PAL collaboration is designing a stripline BPM system for the LINAC for the XFEL project. This consists of 145 ADC and RTMs all packaged into 17 microTCA crates that consists of power modules. Both systems have new RTM board that have been commission or are under testing. We will talk about lessons learned in working with large collaboration.
        Speaker: Andrew Young (SLAC)
        Slides
    • 15:45 16:15
      Coffee 30m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
    • 16:15 17:45
      Session 8 CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Convener: Mr Vollrath Dirksen (N.A.T. GmbH)
      • 16:15
        Data Acquisition Toolset 15m
        The paper outlines DMA engine and supporting software designed to provide flexible use of data acquisition sub-systems for both research and industry.
        Speaker: Mr Ian Shearer (VadaTech Ltd)
        Slides
      • 16:30
        MTCA hardware management integration into the DOOCS control system. 15m
        The Micro Telecommunications Computing Architecture (MTCA) standard provides extensive management, monitoring and diagnostics functionality. The hardware management is based on the Intelligent Platform Management Interface (IPMI). N.A.T provides Java based GUI for visualisation and management of single MTCA crates. The integration of IPMI interface into DOOCS system gives the possibilty to monitor and control hundreds of crates and modules during operation. A DOOCS server communicates to MCH via IPMI over LAN interface and provides overall management functionality for the DOOCS control system.
        Speaker: Mr Vahan Petrosyan (DESY)
        Slides
      • 16:45
        Experience of creating and using Linux Universal PCI Express Device Drivers for MTCA 15m
        The PCI Express standard is currently the most widely used architecture. The MTCA as well as the majority of architectures today use the PCI Express as a central bus of data transmissions. In order to take full advantage of PCI Express enhanced features, more robust device drivers are required. Over the time the support of the increasing number of Device Drivers from different providers is becoming cumbersome without taking into account the different API provided which leads to difficulties for programmers. The Linux Device Driver Model allows us to split PCI Express Device Driver into multiple parts. The low level Driver provides all basic PCI Express and MTCA common functionality. The top level Device Driver of the current device uses common part provided by the low level Driver and adds device specific functionality if needed. Such flexibility will facilitate the tasks of creation and supporting of the Device Drivers, on the other hand it will lead to the principle ”write for one use for all” at the level of user programming, as well as the easy integration of the new Hardware into existing software infrastructures. Our experience of creating and using stacked PCI Express device drivers will be presented.
        Speaker: Mr Ludwig Petrosyan (DESY)
        Slides
      • 17:00
        LINUX general purpose PCIe driver for MTCA 15m
        Micro Telecommunications Computing Architecture (MTCA) is the new generation system, which should allow more stable and reliable control of the accelerator facilities such as the FLASH, the European XFEL, the PITZ and etc. Software development for MTCA devices is among the important tasks. It is undeniable that user space software development is preferable to kernel space software development. Therefore it is worthwhile to engage couple of years in the development of kernel space general purpose driver based on MTCA standards. Ultimately only user space software will be required to adopt new MTCA devices. The design and the development of the general driver started in 2013 with the objective of finally creating a driver that is able to handle as many MTCA devices as possible. The following rule is always kept: if a generalization of any functionality leads to penalty in performance or increase in memory usage or too complicated code is abandoned. In the case a device is not possible to be handled by this driver due to device very specific functionality, driver stacking can be used. The driver can be parent driver for specific device driver. This means for specific device driver only specific functionalities should be implemented with less coding. Some consideration will be presented about which kind of standard registers adding to MTCA standard could be helpful to make this kind of driver more complete. The driver already has use cases: a) PITZ timing devices, b) SIS8300 ADC board from Struck. After presenting the activity on this on 2014 MTCA workshop, collaboration was started with colleagues from Hamburg, who are busy on PCIE universal driver development for MTCA. A lot of development and investigations together have been done. The functionalities implemented so far, a comparison of different DMA schemas, and the performance analysis for some generalized functionalities also will be presented.
        Speaker: Dr Davit Kalantaryan (DESY)
        Slides
      • 17:15
        Firmware Upgrade Framework for MTCA.4 15m
        Every MTCA.4 system includes dozens of various, programmable devices. Besides management controller (MMC) most of the modules are equipped with devices like FPGA, MCU or DSP acting as payload controllers. During firmware development particular devices are reprogrammed using dedicated developer tools and programmers. However, upgrading of the modules one by one or connecting separate programmers for every device is not acceptable in final production system. The situation is especially difficult when the system is composed of hundreds of modules and installed in not accessible place as is the case with control system of XFEL. The presentation shows framework developed at DESY for the needs of remote firmware upgrade in MTCA.4 systems. It is mainly dedicated for programming of non-volatile memories for FPGA devices, because they are most commonly used in modules installed at FLASH and XFEL experiments. The framework allows to program both SPI and JTAG memories. It consists of two main parts: IP core for FPGA responsible for memory programming and software tools (application and scripts) for initialization and supervising of firmware upgrade process. The communication between hardware and software components is based on PCIe interface.
        Speaker: Mr Piotr Perek (Lodz University of Technology, Department of Microelectronics and Computer Science)
        Slides
      • 17:30
        Update on MicroTCA.4 User Tool Kit (MTCA4U) 15m
        The DESY MicroTCA.4 User Tool Kit (MTCA4U) provides a fast and easy way for the development of control applications with MicroTCA.4. The tool kit consists of three major components: A Linux kernel module (driver), a C++ API for accessing the MicroTCA.4 devices and a control system interface layer. Handy tools like python bindings and command line tools offer easy scripting for swift development of new control applications. Recently, C++ API has been restructured to introduce better hardware abstraction through a Device Factory interface. This provides flexibility to transparently use different devices like PCI-Express, a newly introduced register-based communication over the Ethernet or functional mocks for software tests.
        Speaker: Mr Nadeem Shehzad (DESY)
        Slides
    • 17:45 18:00
      Closing Remarks 15m CFEL

      CFEL

      DESY

      Building 99, Notkestraße 85, 22607 Hamburg
      Speaker: Dr Holger Schlarb (DESY)